參數(shù)資料
型號(hào)： DS2722-F-05
英文描述： 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
中文描述： 900MHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 463K
代理商： DS2722-F-05
ML2722
DS2722-F-05
FINAL DATASHEET
DECEMBER 2003
4
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional device operation is not implied.
VDD, VCC5.................................................................................................................................................................6.0 V
VSS, GND..............................................................................................................................................................0 ± 0.3V
Junction Temperature ...............................................................................................................................................150°C
Storage Temperature Range.......................................................................................................................-65°C to 150°C
Lead Temperature (Soldering, 10s) ..........................................................................................................................260°C
OPERATING CONDITIONS
Normal Temperature Range..........................................................................................................................-10°C to 60°C
VCC5 Range...................................................................................................................................................2.7V to 4.5V
Thermal Resistance (
θ
JA
) .................................................................................................................................... 100°C/W
VDD Range (VCC5 = VDD)............................................................................................................................2.7V to 4.5V
Unless otherwise specified, VCC5 & VDD = 2.7V to 3.8V, T
A
= Operating Temperature Range (Note 1) 6.144 or
12.288MHz reference frequency input
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER CONSUMPTION
I
STBY
All Circuits, Standby Mode
10
100
μ
A
I
RX,
I
TX
Receive or Transmit Mode
T
A
= 25°C, VCC5 & VDD = 3.3V
30
50
63.5
mA
I
RX,
I
TX
Receive or Transmit Mode
T
A
= Operating Temperature Range
20
50
70
mA
SYNTHESIZER
f
C
LO output frequency
In 512 KHz steps
902
928
MHz
Φ
N
Phase noise at driver output
1.2 MHz
3 MHz
>7 MHz
VCO phase locked, loop bandwidth
50KHz. Discontinuities, other than
reference spurs, not allowed.
-100
-120
-125
dBc/Hz
f
REF
LO PLL reference frequency at
phase detector
PLL main divider input is at 1.83 GHz
1.024
MHz
N
LO division range integer
PLL divider limits
1024
4093
Count
I
P
LO charge pump sink/source
current
5.5
mA
t
TX2RX
LO lock up time for
Transmit/Receive frequency
change
From RXON asserted
50
μ
s
t
FH
LO lock up time for channel
switch
From EN asserted, any channel
change in 902 to 928 MHz band
100
μ
s
t
WAKE
LO lock up time from sleep
From XCEN, PLL dividers
programmed
240
μ
s
V
FREF
Reference signal input level
6.144 or 12.288MHz sine wave,
capacitively coupled
2.0
3.0
Vp-p
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