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參數(shù)資料
| 型號： | DS2722-F-05 |
| 英文描述： | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| 中文描述： | 900MHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 463K |
| 代理商： | DS2722-F-05 |
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ML2722
DS2722-F-05
FINAL DATASHEET
DECEMBER 2003
11
PIN
SIGNAL
NAME
I/O
FUNCTION
DIAGRAM
7
TPC/TPQ
O (open
drain)
Transmit power control output. This
open-drain output is pulled low when the
TPC bit in serial register #0 is set.
Transitions on TPC are synchronized to
the falling edge of RXON. In analog test
modes, this pin and the RSSI output
become test access points controlled by
the serial control bus.
31
VSS
VDD
100
7
TPC/TPQ
8
TPQ
MUX
VSS
8
TPC
MUX
TPC
9
REF
I
Input for the 12.288 MHz or 6.144 MHz
reference frequency. This input is used
as the reference frequency for the PLL
and as a calibration frequency for the on-
chip filters. This is a self-biased CMOS
input that is designed to be driven either
by an AC-coupled sine wave.
9
VSS
REF
VCC5
24
8
40k
40k
11
QPO
O
Charge Pump Output of the phase
detector. This is connected to the
external PLL loop filter.
10
VSS
R
VCC1
11
QPO
8
VCC5
24
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