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參數(shù)資料
| 型號： | DS2722-F-05 |
| 英文描述： | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| 中文描述： | 900MHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 463K |
| 代理商： | DS2722-F-05 |
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ML2722
DS2722-F-05
FINAL DATASHEET
DECEMBER 2003
20
CONTROL INTERFACES AND REGISTER DESCRIPTIONS
REGISTER INFORMATION
A unidirectional 3-wire serial bus sets the ML2722’s transceiver parameters and programs the PLL circuits.
Programming is performed by entering 16-bit words into the ML2722 serial interface. Three 16-bit registers are
partitioned such that 14 bits are dedicated for data to program the operation and two bits identify the register address.
The three registers are:
§
Register 0:
PLL Configuration
§
Register 1:
Channel Frequency Data
§
Register 2:
Internal Test Access
Figure 5 shows a register map. Table 4 through Table 6 provide detailed diagrams of the register organization: Table 4
and Table 5 outline the PLL configuration and channel frequency registers, and Table 6 displays the filter tuning and test
mode register.
14-bit Data
MSB
DB12
Res.
2-bit Address
Res.
DB13
B15
B14
DB11
Res.
B13
DB10
B12
DB9
B11
DB8
B10
DB7
B9
DB6
B8
DB5
B7
DB4
B6
DB3
B5
DB2
RXCL
B4
DB1
B3
DB0
B2
ADR1
B1
ADR0
B0
Res.
Res.
Res.
Res.
Res.
TPC
TXCL
LOL
RD0
QPP
0
0
14-bit Data
2-bit Address
Res.
DB13
MSB
B15
DB12
Res.
B14
DB11
CHQ11
B13
DB10
CHQ10
B12
DB9
CHQ9
B11
DB8
CHQ8
B10
DB7
CHQ7
B9
DB6
CHQ6
B8
DB5
CHQ5
B7
DB4
CHQ4
B6
DB3
CHQ3
B5
DB2
CHQ2
B4
DB1
CHQ1
B3
DB0
CHQ0
B2
ADR1
B1
ADR0
B0
0
1
14-bit Data
2-bit Address
Res.
DB13
MSB
B15
DB12
Res.
B14
DB11
Res.
B13
DB10
B12
DB9
B11
DB8
B10
DB7
B9
DB6
B8
DB5
DTM2
B7
DB4
DTM1
B6
DB3
DTM0
B5
DB2
ATM2
B4
DB1
ATM1
B3
DB0
ATM0
B2
ADR1
B1
ADR0
B0
Res.
Res.
Res.
Res.
Res.
1
0
Figure 5. Register Organization
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