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參數(shù)資料
| 型號： | DS2722-F-05 |
| 英文描述： | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| 中文描述： | 900MHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 463K |
| 代理商： | DS2722-F-05 |
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ML2722
DS2722-F-05
FINAL DATASHEET
DECEMBER 2003
22
DATA BIT
NAME
DESCRIPTION
USE
B15 (MSB) / DB13
Reserved
B14 / DB12
Reserved
B13 / DB11
Reserved
B12 / DB10
Reserved
B11 / DB9
Reserved
B10 / DB8
Reserved
B9 / DB7
Reserved
B8 / DB6
Reserved
Reserved
Set all bits to 0 (zero)
B7 / DB5
DTM2
B6 / DB4
DTM1
B5 / DB3
DTM0
Digital Test Control Bits
See Table 15
B4 / DB2
ATM2
B3 / DB1
ATM 1
B2 / DB0
ATM 0
Analog Test Control Bits
See Table 14
B1 / ADB1
ADR1
MSB Address Bit
ADR1 = 1
B0 (LSB) / ADB0
ADR0
LSB Address Bit
ADR0 = 0
Table 6. Register 2 – Test Mode Register
CONTROL REGISTER DESCRIPTIONS
Power-On State
All register values are set to 0 (zero) on Power Up. Power up is defined as occurring when VDD (pin 31) =
2.0V
(typical). The register default values are valid after power up. The PLL divide ratio and PLL configuration registers must
be programmed before XCEN is asserted for the first time.
Address and Data Bits (ADR)
Each of the three registers are identically configured. Each is divided into a fourteen (14) bit data field and a two (2) bit
address field. The 16 bits are input serially (see Figure 5) with the 14 data bits, most significant bit (DB13) first followed
by the two address bits, most significant bit (ADR1) first. The last 16 bits clocked into the ML2722 will be loaded into the
specified register. Loading less than 16 bits into any register will cause unpredictable device functionality.
RES Bit Locations (Reserved)
Bits identified as reserved must always have a logic 0 (zero) value for correct device operation. Power-on reset clears
all reserved bits to zero. Each reserved bit must be programmed to logic zero whenever any of the three registers are
reprogrammed.
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