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參數(shù)資料
| 型號： | DS2722-F-05 |
| 英文描述： | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| 中文描述： | 900MHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 463K |
| 代理商： | DS2722-F-05 |
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ML2722
DS2722-F-05
FINAL DATASHEET
DECEMBER 2003
26
REF is the master reference frequency for the transceiver. It supplies the frequency reference for the RF channel
frequency and the filter tuning. The REF pin is a CMOS input with internal biasing resistors. It can be AC coupled
through a 470pF coupling capacitor to a sine wave source of at least 2.0V peak-to-peak. The PLL comparison and the
IF filter center frequency are both equal to the REF input frequency divided by either 6 or 12, depending on the setting
of the RDIV bit in the PLL configuration control word. The IF filter and data filter bandwidths track the IF filter center
frequency.
The Received Signal Strength Indicator (RSSI) pin supplies a voltage indicating the amplitude of the received RF signal.
It is normally connected to the input of a low-speed ADC on an external baseband IC, and is used during channel
scanning to detect clear channels on which the radio may transmit. The RSSI voltage is proportional to the logarithm of
the received power level. A voltage of 0V to 2.7V typically corresponds to an RF input power of –95 to –20dBm with a
nominal slope of 35mV/dB.
CONTROL OUTPUTS TO THE PA – PAON AND TPC
The ML2722 has two output pins to control and sequence the power amplifier – PAON and TPC (see Figure 6).
Figure 6. Power Amplifier Interface
The PAON (PA control) is a CMOS output to control an off-chip RF PA (power amplifier). It outputs a logic high when the
PA should be enabled, and a logic low at all other times. This output is inhibited if the PLL fails to lock, or the power
supply to the ML2722 falls below 2.6V. The PLL lock detect or low voltage signals are latched, so that the transmitter is
inhibited for the entire transmit time slot. These latches are reset at the end of the transmit time slot, so that the ML2722
will transmit in the next time slot following a transient fault condition.
The TPC/TPQ (pin 7) is an open drain output intended for transmit power control. It is controlled by the TPC bit in serial
bus register 0. This bit can be changed at any time, but the TPC pin will not change state until the beginning of the next
transmit time slot, triggered by a falling edge on RXON. This pin interfaces to an external PA power control input via a
resistor network to set the output power level.
In analog test modes the RSSI/TPI (pin 28) and TPC/TPQ (pin 7) become analog test access ports that allow the user
to observe internal signals in the ML2722.
RF INTERFACES
The RRFI receive input (pin 21) and the TRFO transmit output (pin 23) are the only RF I/O pins. The RRFI pin requires
a simple impedance matching network for best input noise figure, and the TRFO pin is matched to 50
by an AC
coupling capacitor. The associated RF input and output ground pins must have direct connections to an RF ground
plane, and the RF block supply pins must be well decoupled to the RF ground pins.
SYMBOL
PARAMETER
TIME/
m
S
t1
RXON falling edge to PAON rising edge
62.5
t2
RXON rising edge to PLL recalibration
6.5
t3
RXON rising edge to receive mode
70
t4
RXON rising edge to PAON falling edge
< 0.1
f
S
11
GHZ
MAG
ANGLE
0.9
0.757
-83.0
RRFI S-PARAMETERS AT 3.3 V,
OPERATING TEMPERATURE 25
O
C
Table 16. Typical Receive RF Input
f
S
11
GHZ
MAG
ANGLE
0.9
0.208
139.5
TRFO S-PARAMETERS AT 3.3 V,
OPERATING TEMPERATURE 25
O
C
Table 17. Typical Transmit RF Output
t1
t2
t3
t4
RXON
Internal
PLLEN
PAON
Output from
TRFO
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