參數(shù)資料
型號: DS2482-800
英文描述: Eight-Channel 1-Wire Master
中文描述: 八通道1-Wire主控制器
文件頁數(shù): 4/22頁
文件大?。?/td> 261K
代理商: DS2482-800
DS2482-800: Eight-Channel 1-Wire Master
4 of 22
PIN DESCRIPTION
Note 1:
Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at
400KHz in Overdrive.
With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the
passive pullup on threshold V
IL1
may not be reached in the available time. With Overdrive speed the
capacitive load on the 1-Wire bus must not exceed 300pF.
Active pullup guaranteed to turn on between V
IL1MAX
and V
IH1MIN
.
Active or resistive pullup choice is configurable.
Fall time high to low (t
F1
) is derived from PD
SRC,
referenced from 0.9 × V
CC
to 0.1 × V
CC
.
These values apply at full load, i. e., 1nF at standard speed and 0.3nF at Overdrive speed. For
reduced load, the pulldown slew rate is slightly faster.
Presence pulse masking only applies to standard speed.
All I2C timing values are referred to V
IHmin
and V
ILmax
levels.
Applies to SDA, SCL, and AD0, AD1, AD2.
I/O pins of the DS2482 do not obstruct the SDA and SCL lines if V
CC
is switched off.
The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V
IHmin
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD
:
DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
t
SU
:
DAT
250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + t
SU
:
DAT
= 1000 + 250 = 1250ns (according to the
standard-mode I2C-bus specification) before the SCL line is released.
C
B
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I2C-Bus Specification v2.1 are allowed.
I2C communication should not take place for the max t
OSCWUP
time following a power-on reset.
Except for t
F1
, all 1-Wire timing specifications and t
APUOT
are derived from the same timing circuit.
Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of
these parameters deviate from their typical value in the same direction and by the same degree.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
IO3
SCL
SDA
VCC
NC
AD2
AD1
AD0
IO7
IO6
IO5
IO4
GND
IO0
IO1
IO2
FUNCTION
IO Driver for 1-Wire Line #3
I2C Serial Clock Input; must be tied to VCC through a pullup resistor.
I2C Serial Data Input/Output; must be tied to VCC through a pullup resistor.
Power Supply Input
Not Connected
I2C Address Inputs; must be tied to VCC or GND. These inputs determine the I2C slave
address of the device, see Figure 9.
IO Driver for 1-Wire Line #7
IO Driver for 1-Wire Line #6
IO Driver for 1-Wire Line #5
IO Driver for 1-Wire Line #4
Ground Reference
IO Driver for 1-Wire Line #0
IO Driver for 1-Wire Line #1
IO Driver for 1-Wire Line #2
相關(guān)PDF資料
PDF描述
DS2482-100 Single-Channel 1-Wire Master
DS2482S-100 Single-Channel 1-Wire Master
DS2482S-800 Eight-Channel 1-Wire Master
DS2502-E48 48-Bit Node Address Chip
DS26401 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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