參數(shù)資料
型號: DS2482-800
英文描述: Eight-Channel 1-Wire Master
中文描述: 八通道1-Wire主控制器
文件頁數(shù): 3/22頁
文件大?。?/td> 261K
代理商: DS2482-800
DS2482-800: Eight-Channel 1-Wire Master
3 of 22
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
(Note 7)
(Note 7)
60
7.1
5.0
2.8
570
68.4
66.5
7.1
7.6
0.7
554.8
70.3
9.5
57
64
7.5
5.3
3.0
600
72
70
7.5
8
0.75
584
74
10
60
68
7.9
5.6
3.2
630
75.6
73.5
7.9
8.4
0.8
613.2
77.7
10.5
63
Write 0 Low Time
t
W0L
μs
Write 0 Recovery Time
t
REC0
μs
Reset Low Time
t
RSTL
μs
Presence-Detect Sample Time
t
MSP
μs
Sampling for Short and
Interrupt
t
SI
μs
Reset High Time
t
RSTH
μs
Presence Pulse Mask Start
Presence Pulse Mask Stop
I2C-Pins (Note 8) See Figure 10
t
ppm1
t
ppm2
μs
μs
V
CC
= 2.9V to 3.7V
0.25 ×
V
CC
0.22 ×
V
CC
V
CC
+
0.5V
LOW Level Input Voltage
V
IL
V
CC
= 4.5V to 5.5V
-0.5
V
HIGH Level Input Voltage
V
IH
0.7 ×
V
CC
0.05 ×
V
CC
V
Hysteresis of Schmitt Trigger
Inputs
LOW Level Output Voltage at
3mA Sink Current
Output Fall Time from V
Ihmin
to
V
ILmax
with a Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes that are
Suppressed by the Input Filter
Input Current Each I/O Pin with
an Input Voltage Between
0.1V
CCmax
and 0.9V
CCmax
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warm-Up Time
V
hys
V
V
OL
0.4
V
t
of
60
250
ns
t
SP
SDA and SCL pins only
50
ns
I
i
(Notes 9, 10)
-10
10
μA
C
i
f
SCL
(Note 9)
10
400
pF
kHz
0
t
HD:STA
0.6
μs
t
LOW
t
HIGH
1.3
0.6
μs
μs
t
SU:STA
0.6
μs
t
HD:DAT
t
SU:DAT
t
SU:STO
(Notes 11, 12)
(Note 13)
0.9
μs
ns
μs
250
0.6
t
BUF
1.3
μs
C
b
(Note 14)
400
pF
t
OSCWUP
(Note 15)
100
μs
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