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參數(shù)資料
| 型號： | DS2450S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONVERTER A/D QUAD 1-W 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Jul/12 |
| 標準包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
DS2450
4 of 24
64-BIT LASERED ROM Figure 3
1-WIRE CRC-GENERATOR Figure 4
DEVICE REGISTERS
All registers of the DS2450 are mapped into a linear memory range of 24 adjacent bytes organized as
three 8-byte pages. The first page, called conversion read-out, contains the memory area where the chip-
internal logic places the results of a conversion for the bus master to read. Starting with channel A at the
lowest address, each channel has an area of 16 bits assigned for the conversion result, as shown in Figure
5a. The power-on default for the conversion read-out registers is all zeros. Regardless of the resolution
requested, the most significant bit of the conversion is always at the same bit position. If less than 16-bit
resolution is requested, the least significant bits of the conversion result will be filled with zeros in order
to always generate a 16-bit result. For applications that require less than four analog inputs, one should
start using input D for the first channel, input C for the second one, etc. The advantage is that when
reading the conversion results one reaches the end of the page and with it the CRC16 sooner and
minimizes the traffic on the 1-Wire bus. For more details on reading please refer to the Read Memory
command description.
MEMORY MAP PAGE 0, CONVERSION READ-OUT
Figure 5a
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00
A
LSBIT A
01
MSBIT A
A
02
B
LSBIT B
03
MSBIT B
B
04
C
LSBIT C
05
MSBIT C
C
06
D
LSBIT D
07
MSBIT D
D
The control and status information for all channels is located in memory page 1 (Figure 5b). As for the
conversion read-out, each channel has assigned 16 bits. The four least significant bits, called RC3 to
RC0, are an unsigned binary number that represents the number of bits to be converted. A code of 1111
(15 decimal) will generate a 15-bit result. For a full 16-bit conversion the code number needs to be 0000.
The next two bits beyond RC3 will always read 0. They have no function and cannot be changed to 1s.
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