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參數(shù)資料
| 型號(hào)： | DS2450S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONVERTER A/D QUAD 1-W 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Jul/12 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極 |
DS2450
21 of 24
CRC HARDWARE DESCRIPTION AND POLYNOMIAL
Figure 12
CRC-GENERATION
With the DS2450 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is a 8-
bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC
value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2450 to
determine if the ROM data has been received error-free by the bus master. The equivalent polynomial
function of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC is received in the true (non inverted) form
when reading the ROM of the DS2450. It is computed once at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16 polynomial function X16
+ X15 + X2 + 1. This CRC is used to safeguard data when reading from or writing to the device’s
memory. It is the same type of CRC as is used with NV RAM based iButtons to safeguard data packets
of the iButton File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned in the
complemented (inverted) form. A CRC-generator inside the DS2450 chip (Figure 12) will calculate a
new 16-bit CRC at every situation shown in the command flow chart of Figure 6.
The DS2450 provides this CRC value to the bus master to validate the transfer of command, address, and
data to and from the bus master. When reading the memory, the 16-bit CRC is transmitted when the end
of each 8-byte memory page is reached. At the initial pass through the Read Memory flow chart the 16-
bit CRC will be generated by clearing the CRC-generator, shifting in the command byte, low address,
high address and the data bytes beginning at the first addressed memory location and continuing until the
last byte of the addressed memory page is reached. Subsequent passes through the Read Memory flow
chart will generate a 16-bit CRC that is the result of clearing the CRC-generator and then shifting in the
new data bytes starting at the first byte of the next page and continuing until the last byte of the page is
reached.
When writing to the DS2450, the bus master receives a 16-bit CRC to verify the correctness of the data
transfer before the device copies the data byte to its memory. With the initial pass through the Write
Memory flow chart the 16-bit CRC will be generated by clearing the CRC-generator, shifting in the
command, address low, address high and the data byte. Subsequent passes through the Write Memory
flow chart due to the DS2450 automatically incrementing its address counter will generate an 16-bit CRC
that is the result of loading (not shifting) the new (incremented) address into the CRC-generator and then
shifting in the new data byte.
For more details on generating CRC values including example implementations in both hardware and
software, see the Book of DS19xx iButton Standards.
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