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參數(shù)資料
| 型號： | DS2450S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/25頁 |
| 文件大小： | 0K |
| 描述： | IC CONVERTER A/D QUAD 1-W 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Jul/12 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
DS2450
19 of 24
INITIALIZATION PROCEDURE “RESET AND PRESENCE PLUSES” Figure 10
*IN ORDER NOT TO MASK INTERRUPT SIGNALING BY OTHER DEVICES ON THE 1-WIRE BUS, tRSTL + tR
SHOULD ALWAYS BE LESS THAN 960 μs
**INCLUDES RECOVERY TIME
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2450 to the master
by triggering a delay circuit in the DS2450. During write time slots, the delay circuit determines when
the DS2450 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay
circuit determines how long the DS2450 will hold the data line low overriding the 1 generated by the
master. If the data bit is a “1”, the device will leave the read data time slot unchanged.
READ/WRITE TIME DIAGRAM
Figure 11
Write-one Time Slot
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