
DS21455/DS21458 Quad T1/E1/J1 Transceivers
41 of 270
6. PARALLEL PORT
The transceiver is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The transceiver can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in
the
AC Electrical Characteristics
for more details.
6.1 Register Map
Table 6-1. REGISTER MAP SORTED BY ADDRESS
ADDRESS
REGISTER NAME
REGISTER
ABBREVIATION
MSTRREG
IOCR1
IOCR2
T1RCR1
T1RCR2
T1TCR1
T1TCR2
T1CCR1
SSIE1
SSIE2
SSIE3
SSIE4
T1RDMR1
T1RDMR2
T1RDMR3
IDR
INFO1
INFO2
INFO3
—
IIR1
IIR2
SR1
IMR1
SR2
IMR2
SR3
IMR3
SR4
IMR4
SR5
IMR5
SR6
IMR6
SR7
IMR7
SR8
IMR8
SR9
IMR9
PCPR
PCDR1
PAGE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
Master Mode Register
I/O Configuration Register 1
I/O Configuration Register 2
T1 Receive Control Register 1
T1 Receive Control Register 2
T1 Transmit Control Register 1
T1 Transmit Control Register 2
T1 Common Control Register 1
Software Signaling Insertion Enable 1
Software Signaling Insertion Enable 2
Software Signaling Insertion Enable 3
Software Signaling Insertion Enable 4
T1 Receive Digital Milliwatt Enable Register 1
T1 Receive Digital Milliwatt Enable Register 2
T1 Receive Digital Milliwatt Enable Register 3
Device Identification Register
Information Register 1
Information Register 2
Information Register 3
—
Interrupt Information Register 1
Interrupt Information Register 2
Status Register 1
Interrupt Mask Register 1
Status Register 2
Interrupt Mask Register 2
Status Register 3
Interrupt Mask Register 3
Status Register 4
Interrupt Mask Register 4
Status Register 5
Interrupt Mask Register 5
Status Register 6
Interrupt Mask Register 6
Status Register 7
Interrupt Mask Register 7
Status Register 8
Interrupt Mask Register 8
Status Register 9
Interrupt Mask Register 9
Per-Channel Pointer Register
Per-Channel Data Register 1
49
78
79
53
53
55
56
57
104
104
105
105
61
61
61
72
62
170
69
—
51
51
171
172
72
73
74
75
76
77
118
118
150
151
150
151
125
126
190
191
46
47