參數(shù)資料
型號： DM9102
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁數(shù)： 54/77頁
文件大小： 459K
代理商： DM9102
DM9102A
Single Chip Fast Ethernet NIC controller
can accept the host commands to start operation. The
general procedure for initialization is described below:
(1) Read/write suitable values for the PCI configuration
registers.
(2) Write CR3 and CR4 to provide the starting address of
each descriptor list.
(3) Write CR0 to set global host bus operation parameters.
(4) Write CR7 to mask causes of unnecessary interrupt.
(5) Write CR6 to set global parameters and start both
receive and transmit processes. Receive and transmit
processes will enter the running state and attempt to acquire
descriptors from the respective descriptor lists.
(6) Wait for any interrupt.
54
Final
Version: DM9102A-DS-F03
August 28, 2000
Data Buffer Processing Algorithm
The data buffer process algorithm is based on the
cooperation of the host and the DM9102A. The host sets
CR3 (receive descriptor base address) and CR4 (transmit
descriptor base address) for the descriptor list initialization.
The DM9102A will start the data buffer transfer after the
descriptor polling and get the ownership. For detailed
processing procedure, please see below.
1. Receive Data Buffer Processing
The DM9102A always attempts to acquire an extra
descriptor in anticipation of the incoming frames. Any
incoming frame size covers a few buffer regions and
descriptors. The following conditions satisfy the descriptor
acquisition attempt:
When start/stop receive sets immediately after being placed
in the running state.
When the DM9102A begins writing frame data to a data
buffer pointed to by the current descriptor and the buffer
ends before the frame ends.
When the DM9102A completes the reception of a frame
and the current receiving descriptor is closed.
When receive process is suspended due to no free buffer for
the DM9102A and a new frame is received.
When receive polling demand is issued. After acquiring the
free descriptor, the DM9102A processes the incoming frame
and places it in the acquired descriptor's data buffer. When
whole the received frame data has been transferred, the
DM9102A will write the status information to the last
descriptor. The same process will repeat until it encounters a
descriptor flagged as being owned by the host. If this occurs,
receive process enters the suspended state and waits the
host to service.
Receive Buffer Management State Transition
Stop
State
Descriptor
Access
Datat
Transfer
Write
Status
Suspended
Start Receive Command Or
Receive Poll Command
Buffer Available
( OWN bit = 1 )
FIFO Threshold
Reached
Frame Fully
Received
Buffer not
Full
Receive Buffer
Unavailable
New Frame Coming Or
Receive Poll Command
Stop Receive Command or
Reset Command
Buffer Full
相關(guān)PDF資料
PDF描述
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*