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參數(shù)資料
| 型號： | DM9102 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single Chip Fast Ethernet NIC controller |
| 中文描述： | 單芯片快速以太網(wǎng)網(wǎng)卡控制器 |
| 文件頁數(shù)： | 37/77頁 |
| 文件大?。?/td> | 459K |
| 代理商： | DM9102 |
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DM9102A
Single Chip Fast Ethernet NIC controller
24:22
ERIT
000,RW
Early Receive Interrupt Threshold
These three bits determine the threshold of the received packet data from RX FIFO
to host memory.
bit24 bit 23 bit22 threshold (percentage)
0 0 0 Disable
0 0 1 12.5%
0 1 0 25.0%
0 1 1 37.5%
1 0 0 50.0%
1 0 1 62.5%
1 1 0 75.0%
1 1 1 87.5%
Final
Version: DM9102A-DS-F03
August 28, 2000
37
21:16
FIFOT
000000
,RW
RX FIFO flow control threshold option
The value of bit21~16 determine the threshold of RX FIFO overflow when in flow
control mode. The exact threshold is 32bytes multiplied by this value.
Transmit pause packet condition control
1 = Indicate Transmit pause packet either CR15<11> or CR15<12> is set.
0 = Indicate Transmit pause packet both CR15<11> and CR15<12> are set.
Transmit pause packet
Set to Transmit pause packet with pause timer = 0000h
Transmit pause packet
Set to Transmit pause packet with pause timer = FFFFh, this bit will be cleared if
packet had transmitted.
Transmit pause packet enable
Set to enable Transmit pause packet if descriptor unavailable
Transmit pause packet enable
Set to enable Transmit pause packet with time = FFFFh if FIFO near overflow, or
with time = 0000h if FIFO empty.
Flow Control Enable
Set to enable the decode of the pause packet.
The latched status of the decode of the pause packet.
Reserved.
Of the decode of the pause packet.
VLAN Capability Enable
It is set to enable the VLAN mode.
Time Interval of Watchdog Release
This bit is used to select the time interval between receive Watchdog timer
expiration until re-enabling of the receive channel. When this bit is set, the time
interval is 40~48 bits time. When this bit is reset, it is 16~24 bits time.
Watchdog Timer Disable
When set, the Watchdog Timer is disabled. Otherwise it is enabled.
Reserved
15
TXPM
0,RW
14
TXP0
0,RW
13
TXPF
0,RW
12
TXPE1
0,RW
11
TXPE2
0.RW
10
FLCE
0,RW
9
8
7
6
RXPS
Reserved
RXPCS
VLAN
0,R/C
0,RO
0,RO
0,RW
5
TWDR
0,RW
4
TWDE
0,RW
3
Reserved
0,RO
相關PDF資料 |
PDF描述 |
|---|---|
| DM9102A | Single Chip Fast Ethernet NIC controller |
| DM9102AF | Single Chip Fast Ethernet NIC controller |
| DM9102AT | Single Chip Fast Ethernet NIC controller |
| DM9108APPLICATIONENGINEERINGNOTESONE | DM9108 Application Engineering notes one |
| DM9108APPLICATIONENGINEERINGNOTESTHREE | DM9108 Application Engineering notes three |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
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