參數(shù)資料
型號(hào)： DM9102
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁數(shù)： 33/77頁
文件大?。?/td> 459K
代理商： DM9102
DM9102A
Single Chip Fast Ethernet NIC controller
11
GPTE
0,RW
General-purpose Timer Expired Enable
This bit is set together with CR7<15>, CR5<11> then it will enable the interrupt for
the condition of the general-purpose timer (described in CR11) expired.
10
TXERE
0,RW
Transmit Early Interrupt Enable
This bit is set together with CR7<16>, CR5<10> then it enables the interrupt of the
early transmit event.
9
RXWTE
0,RW
Receive Watchdog Timer Expired Enable
When this bit and CR7<15>, (CR5<9> are set together, it enable the interrupt of the
condition of the receive watchdog timer expired.
8
RXPSE
0,RW
Receive Process Stopped Enable
When set together with CR7<15> and CR5<8>. This bit is set to enable the
interrupt of receive process stopped condition.
7
RXDUE
0,RW
Receive Buffer Unavailable Enable
When this bit and CR7<15>, CR5<7> are set together, it will enable the interrupt of
receive buffer unavailable condition.
6
RXCIE
0,RW
Receive Complete Interrupt Enable
When this bit and CR7<16>, CR5<6> are set together, it will enable the interrupt of
receive process complete condition.
5
TXFUE
0,RW
Transmit FIFO Underrun Enable
When set together with CR7<15>, CR5<5>, it will enable the interrupt of transmit
FIFO underrun condition.
4
Reserved
0,RO
Reserved
3
TXJTE
0,RW
Transmit Jabber Timer Expired Enable
When this bit and CR7<15>, CR5<3> are set together, it enables the interrupt of
transmit Jabber Timer Expired condition.
2
TXDUE
0,RW
Transmit Buffer Unavailable Enable
When this bit and CR7<16>, CR5<2> are set together, transmit buffer unavailable
interrupt is enabled.
1
TXPSE
0,RW
Transmit Process Stopped Enable
When this bit is set together with CR7<15> and CR5<1>, it will enable the interrupt
of the transmit process stopped
0
TXCIE
0,RW
Transmit Complete Interrupt Enable
When this bit and CR7<16>, CR5<0> are set, the transmit interrupt is enabled.
Final
Version: DM9102A-DS-F03
August 28, 2000
33
9. Statistical Counter Register (CR8)
31
30
29
28
27 26
25
24
23
22
21 20 19
18
17
16
15
14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
Bit
31
Name
RXFU
Default
0,RO
Description
Receive Overflow Counter Overflow
This bit is set when the Purged Packet Counter (RXDU) has an overflow condition.
It is a read only register bit.
Receive Purged Packet Counter
This is a statistic counter to indicate the purged received packet count upon FIFO
overflow.
30:17
RXDU
0,RO
相關(guān)PDF資料
PDF描述
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
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