- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379101 > CYV15G0404RB-BGXC (CYPRESS SEMICONDUCTOR CORP) Independent Clock Quad HOTLink II⑩ Deserializing Reclocker PDF資料下載
參數(shù)資料
| 型號： | CYV15G0404RB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 388K |
| 代理商： | CYV15G0404RB-BGXC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁
CYV15G0404RB
Document #: 38-02102 Rev. *C
Page 21 of 27
CYV15G0404RB AC Electrical Characteristics
Notes
14.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15.The ratio of rise time to falling time must not vary by greater than 2:1.
16.For a given operating frequency, neither rise nor fall specification can be greater than 20% of the clock cycle period or the data sheet maximum time.
17.All transmit AC timing parameters measured with 1ns typical rise time and fall time.
18.Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
19.Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when TRGRATEx = 1) or 1/(f
TRG
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t
B
.
20.The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
cycle cannot be as large as 30%–70%.
21.TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKx± must be within
±
1500 PPM (
±
0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
Parameter
CYV15G0404RB Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx± Clock Output Frequency
t
RXCLKP
RXCLKx± Period = 1/f
RS
t
RXCLKD
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)
t
RXCLKR [14]
RXCLKx± Rise Time
t
RXCLKF [14]
RXCLKx± Fall Time
t
RXDv–[18]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
t
RXDv+[18]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)
f
ROS
RECLKOx Clock Frequency
t
RECLKO
RECLKOx Period = 1/f
ROS
t
RECLKOD
RECLKOx Duty Cycle centered at 60% HIGH time
CYV15G0404RB TRGCLKx Switching Characteristics
Over the Operating Range
f
TRG
TRGCLKx Clock Frequency
TRGCLKx Period = 1/f
REF
t
TRGH
TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)
TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)
t
TRGL
TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)
TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)
t
TRGD[20]
TRGCLKx Duty Cycle
t
TRGR[14, 15, 16, 17]
TRGCLKx Rise Time (20%–80%)
t
TRGF[14, 15, 16, 17]
TRGCLKx Fall Time (20%–80%)
t
TRGRX[21]
TRGCLKx Frequency Referenced to Received Clock Frequency
CYV15G0404RB Bus Configuration Write Timing Characteristics
Over the Operating Range
t
DATAH
Bus Configuration Data Hold
t
DATAS
Bus Configuration Data Setup
t
WRENP
Bus Configuration WREN Pulse Width
CYV15G0404RB JTAG Test Clock Characteristics
Over the Operating Range
f
TCLK
JTAG Test Clock Frequency
t
TCLK
JTAG Test Clock Period
Description
Min
Max
Unit
9.75
6.66
–1.0
0.3
0.3
150
102.56
+1.0
1.2
1.2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
5UI–2.0
[19]
5UI–1.3
[19]
5UI–1.8
[19]
5UI–2.6
[19]
19.5
6.66
–1.9
150
51.28
0
19.5
6.6
5.9
2.9
[14]
5.9
2.9
[14]
30
150
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
%
TRGCLK
70
2
2
–0.15
+0.15
0
10
10
ns
ns
ns
20
MHz
ns
50
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0404RB | Independent Clock Quad HOTLink II Reclocking Deserializer(獨立時鐘，四路HOTLink II時鐘恢復(fù)串并轉(zhuǎn)換器) |
| CYV270M0101EQ | Adaptive Video Cable Equalizer (SOIC) |
| CYV270M0101EQ-SXC | Adaptive Video Cable Equalizer (SOIC) |
| CYW2338 | Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers |
| CYWM6935PAEC | WirelessUSB⑩ LR+PA Radio Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV270101EQ-SXC | 制造商:Cypress Semiconductor 功能描述: |
| CYV270M0101EQ | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Adaptive Video Cable Equalizer |
| CYV270M0101EQ_0710 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Adaptive Video Cable Equalizer |
| CYV270M0101EQ-SXC | 功能描述:多媒體雜項 Std Definition Video Equalizr COM RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
| CYV270M0101EQ-SXCES | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。