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參數(shù)資料
| 型號： | CYV15G0404RB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數(shù)： | 17/27頁 |
| 文件大小： | 388K |
| 代理商： | CYV15G0404RB-BGXC |
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CYV15G0404RB
Document #: 38-02102 Rev. *C
Page 17 of 27
JTAG Support
The CYV15G0404RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
To ensure valid device operation after power-up (including
non-JTAG operation), the JTAG state machine must also be
initialized to a reset state. This must be done in addition to the
device reset (using RESET). Initialize the JTAG state machine
using TRST (assert it LOW and deassert it or leave it
asserted), or by asserting TMS HIGH for at least 5 consecutive
TCLK cycles. This is necessary in order to ensure that the
JTAG controller does not enter any of the test modes after
device power-up. In this JTAG reset state, the rest of the
device will operate normally.
Note
The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
Each 3-Level select input reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.
Table 5. Receive BIST Status Bits
{BISTSTx, RXDx[0],
RXDx[1]}
Description
Receive BIST Status
(Receive BIST = Enabled)
000, 001
010
011
100
101
BIST Data Compare
. Character compared correctly.
BIST Last Good
. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad
.
Last Character of BIST sequence detected invalid.
BIST Start
. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error
. While comparing characters, a mismatch was found in one or more of the character bits.
BIST Wait
. The receiver is comparing characters, but has not yet found the start of BIST character to
enable the LFSR.
110
111
[+] Feedback
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