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參數資料
| 型號： | CYV15G0404RB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數： | 11/27頁 |
| 文件大?。?/td> | 388K |
| 代理商： | CYV15G0404RB-BGXC |
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CYV15G0404RB
Document #: 38-02102 Rev. *C
Page 11 of 27
CYV15G0404RB HOTLink II Operation
The CYV15G0404RB is a highly configurable, independent
clocking, quad-channel reclocking deserializer that supports
reliable transfer of large quantities of digital video data, using
high-speed serial links from multiple sources to multiple desti-
nations. This device supports four 10-bit channels.
CYV15G0404RB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel to accept serial data streams. The
associated INSELx input selects the active Serial Line
Receiver on a channel. The Serial Line Receiver inputs are
differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs must receive a
signal of at least VI
DIFF
> 100 mV, or 200 mV peak-to-peak
differential. Each Line Receiver can be DC or AC coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC coupled to +5V
powered optical modules. The common mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal DC
restoration, to the center of the receiver’s common mode
range, for AC coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (that is, that routed to the clock
and data recovery PLL) is simultaneously monitored for
Analog amplitude above amplitude level selected by
SDASELx
Transition density above the specified limit
Range controls reporting the received data stream inside
normal frequency range (±1500 ppm
[21]
)
Receive channel enabled
Reference clock present
ULCx not asserted.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high noise
environments. The SDASELx latch sets the analog amplitude
level detection via the device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in
Table 1
. This control
input affects the analog monitors for all receive channels. The
Analog Signal Detect monitors are active for the Line Receiver,
as selected by the associated INSELx input.
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If there are no transitions in the data received, the
Detection logic for that channel asserts LFIx.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) samples the
incoming data stream. This logic ensures that the VCO
TDO
3-State LVTTL Output
Test Data Out
. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
LVTTL Input,
internal pull up
LVTTL Input,
internal pull up
TRST
JTAG reset signal
. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
V
CC
GND
+3.3V Power
.
Signal and Power Ground for all internal circuits
.
Pin Definitions
(continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
IO Characteristics
Signal Description
Table 1. Analog Amplitude Detect Valid Signal Levels
[5]
SDASEL
00
01
10
11
Typical Signal with Peak Amplitudes Above
Analog Signal Detector is disabled
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
Note
5. The peak amplitudes listed in this table are for typical waveforms that generally have 3–4 transitions for every ten bits. In a worst case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
[+] Feedback
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