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參數(shù)資料
| 型號： | CYV15G0104 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock HOTLink II?? Serializer and Reclocking Deserializer |
| 中文描述： | 獨立時鐘的HOTLink二？？串行解串器的時鐘重計 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 985K |
| 代理商： | CYV15G0104 |
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PRELIMINARY
CYV15G0104TRB
Document #: 38-02100 Rev. **
Page 21 of 28
CYV15G0104TRB TRGCLKA Switching Characteristics
Over the Operating Range
f
TRG
TRGCLKA Clock Frequency
t
REFCLK
TRGCLKA Period = 1/f
TRG
t
TRGH
TRGCLKA HIGH Time (TRGRATEA = 1)(Half Rate)
TRGCLKA HIGH Time (TRGRATEA = 0)(Full Rate)
t
TRGL
TRGCLKA LOW Time (TRGRATEA = 1)(Half Rate)
TRGCLKA LOW Time (TRGRATEA = 0)(Full Rate)
t
TRGD[23]
TRGCLKA Duty Cycle
t
TRGR [16, 17, 18]
TRGCLKA Rise Time (20%–80%)
t
TRGF[16, 17, 18]
TRGCLKA Fall Time (20%–80%)
t
TRGRX[24]
TRGCLKA Frequency Referenced to Received Clock Frequency
CYV15G0104TRB Bus Configuration Write Timing Characteristics
Over the Operating Range
t
DATAH
Bus Configuration Data Hold
t
DATAS
Bus Configuration Data Setup
t
WRENP
Bus Configuration WREN Pulse Width
CYV15G0104TRB JTAG Test Clock Characteristics
Over the Operating Range
f
TCLK
JTAG Test Clock Frequency
t
TCLK
JTAG Test Clock Period
CYV15G0104TRB Device RESET Characteristics
Over the Operating Range
t
RST
Device RESET Pulse Width
CYV15G0104TRB Transmitter and Reclocker Serial Output Characteristics
Over the Operating Range
Parameter
Description
t
B
Bit Time
t
RISE[16]
CML Output Rise Time 20
80% (CML Test Load)
19.5
6.6
5.9
2.9
[16]
5.9
2.9
[16]
30
150
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
%
70
2
2
–0.15
+0.15
0
ns
ns
ns
10
10
20
MHz
ns
50
30
ns
Condition
Min.
660
50
Max.
5128
270
Unit
ps
ps
SPDSELx =
HIGH
SPDSELx= MID
SPDSELx =LOW
SPDSELx =
HIGH
SPDSELx = MID
SPDSELx =LOW
100
180
50
500
1000
270
ps
ps
ps
t
FALL[16]
CML Output Fall Time 80
20% (CML Test Load)
100
180
500
1000
ps
ps
PLL Characteristics
Parameter
CYV15G0104TRB Transmitter Output PLL Characteristics
t
JTGENSD[16, 25]
Transmit Jitter Generation - SD Data Rate
t
JTGENHD[16, 25]
Transmit Jitter Generation - HD Data Rate
Description
Condition
Min
.
Typ.
Max.
Unit
REFCLKB = 27 MHz
REFCLKB = 148.5
MHz
200
76
ps
ps
t
TXLOCK
Notes:
23. The duty cycle specification is a simultaneous condition with the t
TRGH
and t
TRGL
parameters. This means that at faster character rates the TRGCLKA± duty
cycle cannot be as large as 30%–70%.
24. TRGCLKA± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKA± must be within
±
1500 PPM (
±
0.15%) of the transmitter PLL reference (REFCLK±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
25. While sending BIST data at the corresponding data rate, after 10,000 histogram hits, time referenced to REFCLKB± input.
26. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The
measurement was recorded after 10,000 histogram hits, time referenced to REFCLKB± of the transmit channel.
Transmit PLL lock to REFCLKB±
200
μ
s
CYV15G0104TRB AC Electrical Characteristics
(continued)
Parameter
Description
Min.
Max
Unit
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| CYV15G0104EQ | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Multi Rate Video Cable Equalizer |
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| CYV15G0104TRB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II Serializer and Reclocking Deserializer |
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