參數(shù)資料
型號: CYV15G0403TB-BGXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Independent Clock Quad HOTLink II⑩ Serializer
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256
文件頁數(shù): 1/21頁
文件大小: 324K
代理商: CYV15G0403TB-BGXC
Independent Clock Quad HOTLink II
Serializer
CYV15G0403TB
Cypress Semiconductor Corporation
Document #: 38-02104 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 2, 2007
Features
Second-generation HOTLink
technology
Compliant to SMPTE 292M and SMPTE 259M video
standards
Quad channel video serializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
Supports half-rate and full-rate clocking
Internal phase-locked loops (PLLs) with no external PLL
components
Redundant differential PECL-compatible serial outputs per
channel
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
Synchronous LVTTL parallel interface
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Low-power 2W @ 3.3V typical
Single 3.3V supply
Thermally enhanced BGA
Pb-Free package option available
0.25
μ
BiCMOS technology
Functional Description
The CYV15G0403TB Independent Clock Quad HOTLink II
Serializer is a point-to-point or point-to-multipoint communica-
tions building block enabling transfer of data over a variety of
high-speed serial links including SMPTE 292M and SMPTE
259M video applications. It supports signaling rates in the
range of 195 to 1500 Mbps per serial link. All four channels are
independent and can simultaneously operate at different
rates. Each channel accepts 10-bit parallel characters in an
Input Register and converts them to serial data.
Figure 1
illus-
trates typical connections between independent video
co-processors and corresponding CYV15G0403TB Serializer
and CYV15G0404RB Reclocking Deserializer chips.
The CYV15G0403TB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As
a
second-generation
CYV15G0403TB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices. Each channel of the CYV15G0403TB Quad HOTLink
II device independently accepts scrambled 10-bit transmission
characters. These characters are serialized and output from
dual Positive ECL (PECL) compatible differential trans-
mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock for that channel.
Each channel contains an independent BIST pattern
generator. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each transmit section of this
device, each receive section of a connected HOTLink II
device, and across the interconnecting links.
HOTLink
device,
the
Figure 1. HOTLink II System Connections
V
10
10
10
10
V
10
10
10
10
Serial Links
Independent
Channel
CYV15G0404RB
CYV15G0403TB
Serializer
Independent
Channel
Reclocking Deserializer
Reclocked
Outputs
Reclocked
Outputs
[+] Feedback
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