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參數(shù)資料
| 型號： | CYV15G0104 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock HOTLink II?? Serializer and Reclocking Deserializer |
| 中文描述： | 獨立時鐘的HOTLink二？？串行解串器的時鐘重計 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 985K |
| 代理商： | CYV15G0104 |
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PRELIMINARY
CYV15G0104TRB
Document #: 38-02100 Rev. **
Page 14 of 28
is forced to the WAIT_FOR_BIST state where it monitors the
receive path for the first character of the next BIST sequence.
Power Control
The CYV15G0104TRB supports user control of the powered
up or down state of each transmit and receive channel. The
receive channels are controlled by the RXPLLPDA latch via
the device configuration interface. When RXPLLPDA = 0, the
receive PLL and analog circuitry of the channel is disabled.
The transmit channel is controlled by the TOE1B and the
TOE2B latches via the device configuration interface. The
reclocker function is controlled by the ROE1A and the ROE2A
latches via the device configuration interface. When a driver is
disabled via the configuration interface, it is internally powered
down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic
for that channel is also powered down. When the reclocker
serial drivers are disabled, the reclocker function will be
disabled, but the deserialization logic and parallel outputs will
remain enabled.
Device Reset State
When the CYV15G0104TRB is reset by assertion of RESET,
all state machines, counters, and configuration latches in the
device are initialized to a reset state. See
Table 4
for the
initialize values of the configuration latches.
Following a device reset, it is necessary to enable the transmit
and receive channels used for normal operation. This can be
done by sequencing the appropriate values on the device
configuration interface.
[5]
Device Configuration and Control Interface
The CYV15G0104TRB is highly configurable via the configu-
ration interface. The configuration interface allows the trans-
mitter and reclocker to be configured independently.
Table 4
lists the configuration latches within the device including the
initialization value of the latches upon the assertion of RESET.
Table 5
shows how the latches are mapped in the device.
Each row in the
Table 5
maps to a 7-bit latch bank. There are
6 such write-only latch banks. When WREN = 0, the logic value
in the DATA[6:0] is latched to the latch bank specified by the
values in ADDR[2:0]. The second column of
Table 5
specifies
the channels associated with the corresponding latch bank.
For example, the first three latch banks (0,1 and 2) consist of
configuration bits for the reclocker channel A.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 5, and 6) are the static control latches. The third row of
latches for each channel (address numbers 2 and 7) are the
dynamic control latches that are associated with enabling
dynamic functions within the device. Address numbers 3 and
4 are internal test registers.
Static Latch Values
There are some latches in the table that have a static value
(i.e. 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
Table 4. Device Configuration and Control Latch Descriptions
RXRATEA
Receive Clock Rate Select
. The initialization value of the RXRATEA latch = 1. RXRATEA is used to
select the rate of the RXCLKA± clock output.
When RXRATEA = 1, the RXCLKA± clock outputs are complementary clocks that follow the recovered
clock operating at half the character rate. Data for the associated receive channels should be latched
alternately on the rising edge of RXCLKA+ and RXCLKA–.
When RXRATEA = 0, the RXCLKA± clock outputs are complementary clocks that follow the recovered
clock operating at the character rate. Data for the associated receive channels should be latched on the
rising edge of RXCLKA+ or falling edge of RXCLKA–.
Primary Serial Data Input Signal Detector Amplitude Select
. The initialization value of the
SDASEL1A[1:0] latch = 10. SDASEL1A[1:0] selects the trip point for the detection of a valid signal for
the INA1± Primary Differential Serial Data Inputs.
When SDASEL1A[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1A[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.
When SDASEL1A[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.
When SDASEL1A[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.
Secondary Serial Data Input Signal Detector Amplitude Select
. The initialization value of the
SDASEL2A[1:0] latch = 10. SDASEL2A[1:0] selects the trip point for the detection of a valid signal for
the INA2± Secondary Differential Serial Data Inputs.
When SDASEL2A[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2A[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.
When SDASEL2A[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.
When SDASEL2A[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.
SDASEL1A[1:0]
SDASEL2A[1:0]
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