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參數(shù)資料
| 型號(hào)： | CYV15G0104 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock HOTLink II?? Serializer and Reclocking Deserializer |
| 中文描述： | 獨(dú)立時(shí)鐘的HOTLink二？？串行解串器的時(shí)鐘重計(jì) |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 985K |
| 代理商： | CYV15G0104 |
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PRELIMINARY
CYV15G0104TRB
Document #: 38-02100 Rev. **
Page 19 of 28
AC Test Loads and Waveforms
CYV15G0104TRB AC Electrical Characteristics
V
OLC
Output LOW Voltage
(V
CC
Referenced)
100
differential load
150
differential load
100
differential load
150
differential load
V
CC
– 1.4
V
CC
– 1.4
450
560
V
CC
– 0.7
V
CC
– 0.7
900
1000
V
V
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
mV
mV
Differential Serial Line Receiver Inputs: INA1
±
, INA2
±
V
DIFFs[9]
Input Differential Voltage |(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
VI
COM[11]
Common Mode input range
100
1200
V
CC
mV
V
V
μ
A
μ
A
V
V
CC
– 2.0
V
IN
= V
IHE
Max.
V
IN
= V
ILE
Min.
((V
CC
– 2.0V)+0.5)min,
(V
CC
– 0.5V) max.
1350
–700
+1.25
+3.1
Power Supply
I
CC [12,13]
Typ.
585
Max.
690
Max Power Supply Current
REFCLKB
= MAX
REFCLKB
= 125 MHz
Commercial
mA
I
CC [12,13]
Typical Power Supply Current
Commercial
560
660
mA
CYV15G0104TRB DC Electrical Characteristics
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
(Includes fixture and
probe capacitance)
3.0V
V
th
= 1.4V
≤
270 ps
≤
270 ps
Note 15
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
R2 = 435
C
L
≤
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
(b) CML Output Test Load
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
≤
1 ns
≤
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
Note 14
Note 14
Parameter
CYV15G0104TRB Transmitter LVTTL Switching Characteristics
Over the Operating Range
f
TS
TXCLKB Clock Cycle Frequency
t
TXCLK
TXCLKB Period=1/f
TS
t
TXCLKH[16]
TXCLKB HIGH Time
t
TXCLKL[16]
TXCLKB LOW Time
Notes:
11.
The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
12. Maximum I
is measured with V
CC
= MAX,T
A
= 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
outputs unloaded.
13. Typical I
is measured under similar conditions except with V
= 3.3V, T
= 25°C,with all channels enabled and one Serial Line Driver per channel sending
a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
14. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
15. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
16. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
Description
Min.
Max
Unit
19.5
6.66
2.2
2.2
150
51.28
MHz
ns
ns
ns
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參數(shù)描述 |
|---|---|
| CYV15G0104EQ | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Multi Rate Video Cable Equalizer |
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| CYV15G0104TRB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II Serializer and Reclocking Deserializer |
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