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參數(shù)資料
| 型號： | CYV15G0104 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock HOTLink II?? Serializer and Reclocking Deserializer |
| 中文描述： | 獨立時鐘的HOTLink二？？串行解串器的時鐘重計 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 985K |
| 代理商： | CYV15G0104 |
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PRELIMINARY
CYV15G0104TRB
Document #: 38-02100 Rev. **
Page 16 of 28
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets both channels.
2. Set the static latch banks for the target channel.
3. Set the dynamic bank of latches for the target channel.
Enable the Receive PLL and/or transmit channel. If the
receiver is enabled, set the device for SMPTE data
reception (RXBISTA[1:0] = 01) or BIST data reception
(RXBISTA[1:0] = 10).
4. Reset the Phase Alignment Buffer. [Optional if phase align
buffer is bypassed.]
JTAG Support
The CYV15G0104TRB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs, the
TRGCLKA± input, and the REFCLKB± clock input. The high-
speed serial inputs and outputs are not part of the JTAG test
chain.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0104TRB is ‘0C811069’x.
PABRSTB
Transmit Clock Phase Alignment Buffer Reset
. The initialization value of the PABRSTB latch = 1.
The PABRSTB is used to re-center the Transmit Phase Align Buffer. When the configuration latch
PABRSTB is written as a 0, the phase of the TXCLKB input clock relative to REFCLKB+/- is initialized.
PABRSTB is an asynchronous input, but is sampled by each TXCLKB
↑
to synchronize it to the internal
clock domain. PABRSTB is a self clearing latch. This eliminates the requirement of writing a 1 to complete
the initialization of the Phase Alignment Buffer.
Table 4. Device Configuration and Control Latch Descriptions
(continued)
Table 5. Device Control Latch Configuration Table
ADDR
Channel
Type
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset
Value
0
(000b)
A
S
1
0
X
X
0
0
RXRATEA
1011111
1
(001b)
A
S
SDASEL2A[1]
SDASEL2A[0]
SDASEL1A[1]
SDASEL1A[0]
X
X
TRGRATEA
1010110
2
(010b)
A
D
RXBISTA[1]
RXPLLPDA
RXBISTA[0]
X
ROE2A
ROE1A
X
1011001
3
(011b)
INTERNAL TEST REGISTERS
DO NOT WRITE TO THESE ADDRESSES
4
(100b)
5
(101b)
B
S
X
X
X
X
X
0
RXRATE D
1011111
6
(110b)
B
S
X
X
X
X
0
TXCKSELB
TXRATEB
1010110
7
(111b)
B
D
X
0
X
TXBISTB
TOE2B
TOE1B
PABRSTB
1011001
Table 6. Receive BIST
Status Bits
{BISTSTA, RXDA[0], RXDA[1]}
000, 001
010
011
100
101
Description
Receive BIST Status
(Receive BIST = Enabled)
BIST Data Compare
. Character compared correctly.
BIST Last Good
. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad
.
Last Character of BIST sequence detected invalid.
BIST Start
. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error
. While comparing characters, a mismatch was found in one or more of the
character bits.
BIST Wait
. The receiver is comparing characters. but has not yet found the start of BIST
character to enable the LFSR.
110
111
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