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參數(shù)資料
| 型號： | CYNSE70128 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 19/126頁 |
| 文件大?。?/td> | 3302K |
| 代理商： | CYNSE70128 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 19 of 126
12.2
Table 12-2
lists the CMD bus fields that contain the CYNSE70032 command parameters and their respective cycles. Each
command is described separately in the subsections that follow.
Commands and Command Parameters
12.3
The Read can be a single Read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst
Read of the data (CMD[2] = 1) or mask array locations using an internal autoincrementing address register (RBURADR).
A description of each type is provided in
Table 12-3
. A single-location Read operation lasts six cycles, as shown in
Figure 12-1
.
The burst Read adds two cycles for each successive Read. The SADR[21:19] bits supplied in Read instruction cycle A drive
SADR[21:19] signals during the Read of an SRAM location.
Read Command
Note:
5.
The 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the Learn instruction.
Table 12-2. Command Parameters
Command
Read
CYC
A
8
7
6
5
0
4
0
3
0
2
1
0
0
0
SADR[21]
SADR[20]
SADR[19]
0 = Single
1 = Burst
0 = Single
1 = Burst
0 = Single
1 = Burst
0 = Single
1 = Burst
68-bit or 136-bit: 0
272-bit:
1 in first cycle
0 in second cycle
B
0
0
0
0
0
0
0
0
Write
A
SADR[21]
SADR[20]
SADR[19]
GMR Index [2:0]
0
1
B
0
0
0
GMR Index [2:0]
0
1
Search
A
SADR[21]
SADR[20]
SADR[19]
GMR Index 2:0]
1
0
B
A
B
SSR Index[2:0]
SADR[20]
0
Comparand Register Index
Comparand Register Index
Comparand Register Index
1
1
1
0
1
1
Learn
[5]
SADR[21]
0
SADR[19]
Mode
0: 68-bit
1: 136-bit
Table 12-3. Read Command Parameters
Command Parameter
CMD[2]
0
Read Command
Single Read
Description
Reads a single location of the data array, mask array, external SRAM, or device
registers. All access information is applied on the DQ bus.
Reads a block of locations from the data or mask arrays as a burst. The RBURADR
specifies the starting address and the length of the data transfer from the data or
mask array, and it autoincrements the address for each access. All other access
information is applied on the DQ bus.
Note
. The device registers and external
SRAM can only be read in single-Read mode.
1
Burst Read
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