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參數(shù)資料
| 型號： | CYNSE70128 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 106/126頁 |
| 文件大?。?/td> | 3302K |
| 代理商： | CYNSE70128 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 106 of 126
15.6
SRAM Write enables write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed into the device configuration register. The following explains the SRAM Write operation
accomplished through a table of only one device with the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and
LDEV = 1.
Figure 15-8
shows the timing diagram. For the following description, the selected device refers to the only device in
the table as this is the only device that will be accessed.
Cycle 1A
: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle.
Note
. CMD[2] must be set to 0 for SRAM Write,
because burst Writes into the SRAM are not supported.
Cycle 1B
: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address.
Note
. CMD[2] must be set to 0 for SRAM Write, because burst
Writes into the SRAM are not supported.
Cycle 2
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
Cycle 3
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
At the end of cycle 3, a new command can begin. The write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
SRAM Write with a Table of One Device
cycle
1
CLK2X
CE_L
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
PHS_L
SADR[21:0]
SSF
SSV
1
0
0
CMDV
CMD[1:0]
CMD[8:2]
00
Read
A B
Address
DQ
z
1
WE_L
OE_L
0
ALE_L
1
z
z
1
z
ACK
z
1
1
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1
Figure 15-7. SRAM Readthrough Device Number 0 in a Bank of 31 Devices
(Device Number 30 Timing)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYNSE70256 | Network Processing |
| CZET101 | Clock Driver |
| CZEU101 | Quad Peripheral Driver |
| CZEZ101 | Triple Peripheral Driver |
| CZSP103 | Voltage Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70128-83BGC | 制造商:Cypress Semiconductor 功能描述:NETWORK SEARCH ENGINE 388BGA - Trays |
| CYNSE70128-83BGI | 制造商:Cypress Semiconductor 功能描述:NETWORK SEARCH ENGINE 388BGA - Trays |
| CYNSE70129HV-200BGC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70131-250BBC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70131A-250BBC | 制造商:Cypress Semiconductor 功能描述: |
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