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參數(shù)資料
| 型號： | CYDD04S18V18-167BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 DUAL-PORT SRAM, 9 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256 |
| 文件頁數(shù)： | 6/53頁 |
| 文件大?。?/td> | 2422K |
| 代理商： | CYDD04S18V18-167BBI |
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FullFlex
Document #: 38-06072 Rev. *I
Page 14 of 53
The mask register value affects the Counter Increment and
Counter Reset operations by preventing the corresponding
bits of the counter register from changing. It also affects the
counter interrupt output (CNTINT). The mask register is only
changed by Mask Reset, Mask Load, and MRST. The Mask
Load operation loads the value of the address bus into the
mask register. The mask register defines the counting range
of the counter register. The mask register is divided into two or
three consecutive regions. Zero or more “0s” define the
masked region and one or more “1s” define the unmasked
portion of the counter register. The counter register may only
be divided into up to three regions. The region containing the
least significant bits must be no more than two “0s”. Bits one
and zero may be “10” respectively, masking the least signif-
icant counter bit and causing the counter to increment by two
instead of one. If bits one and zero are “00”, the two least
significant bits are masked and the counter will increment by
four instead of one. For example, in the case of a 256Kx72
configuration, a mask register value of 003FC divides the
mask register into three regions. With bit 0 being the least
significant bit and bit 17 being the most significant bit, the two
least significant bits are masked, the next eight bits are
unmasked, and the remaining bits are masked.
The mirror register is used to reload the counter register on
retransmit operations (see “retransmit” below) and wrap
functions (see “counter increment” below). The last value
loaded into the counter register is stored in the mirror register.
The mirror register is only changed by master reset (MRST),
Counter Reset, and Counter Load.
Table 8 summarizes the operations of these registers and the
required input control signals. All signals except MRST are
synchronized to the ports clock.
Counter Load Operation[1]
The address counter and mirror registers are both loaded with
the address value presented on the address lines. This value
ranges from 0 to FFFFF.
Mask Load Operation[1]
The mask register is loaded with the address value presented
on the address bus. This value ranges from 0 to FFFFF though
not all values permit correct increment operations. Permitted
values are in the form of 2n–1, 2n–2, or 2n–4. The counter
register can only be segmented in up to three regions. From
the most significant bit to the least significant bit, permitted
values have zero or more “0s”, one or more “1s”, and the least
significant two bits can be “11”, “10”, or “00”. Thus FFFFE,
7FFFF, and 03FFC are permitted values but 2FFFF, 03FFA,
and 7FFE4 are not.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. The address will be valid tCA after the
selected number of latency cycles configured by FTSEL. This
is the same as data in SDR mode and one half cycle earlier
than data latency for DDR mode. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 4 shows a block diagram of the logic.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. The address will be valid tCA after the selected
number of latency cycles configured by FTSEL. For pipelined
SDR and DDR mode this is two cycles. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 4 shows a block diagram of the
operation.
Table 8. Burst Counter and Mask Register Control Operation (Any Port) [20,21]
C
MRST CNTRST CNT/MSK CNTEN ADS RET
Operation
Description
X
L
X
Master Reset
Reset address counter to all 0s, mask register
to all 1s, and busy address to all 0’s.
H
L
H
X
Counter Reset
Reset counter and mirror unmasked portion to
all 0s.
H
L
X
Mask Reset
Reset mask register to all 1s.
H
L
X
Counter Load
Load burst counter and mirror with external
address value presented on address lines.
H
L
X
Mask Load
Load mask register with value presented on the
address lines.
H
L
H
L
Retransmit
Load counter with value in the mirror register
H
L
H
Counter
Increment
Internally increment address counter value.
H
Counter Hold
Constantly hold the address value for multiple
clock cycles.
H
L
H
Counter
Readback
Read out counter internal value on address
lines.
H
L
H
L
H
Mask Readback
Read out mask register value on address lines.
Notes:
20. X” = “Don’t Care”, “H” = HIGH, “L” = LOW.
21. Counter operation and mask register operation is independent of chip enables.
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| CYDD04S18V18-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 128Kx36 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S18V18-167BBXI | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 128Kx36 90nm DDR IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S18V18-200BBXC | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 128Kx36 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S36V18-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 64Kx72 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S36V18-167BBXI | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 64Kx72 90nm DDR IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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