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參數(shù)資料
| 型號： | CYDD04S18V18-167BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 DUAL-PORT SRAM, 9 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256 |
| 文件頁數(shù)： | 4/53頁 |
| 文件大?。?/td> | 2422K |
| 代理商： | CYDD04S18V18-167BBI |
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FullFlex
Document #: 38-06072 Rev. *I
Page 12 of 53
all DLLs on the chip, for information on DLL lock and reset
time, please see the Master Reset section below.
Echo Clocking
As the speed of data increases, on-board delays caused by
parasitics make providing accurate clock trees extremely
difficult. To counter this problem, the FullFlex families incor-
porate Echo Clocks. Echo Clocks are enabled on a per port
basis. The dual-port receives input clocks (C and C for DDR
mode, C for SDR mode) that are used to clock in the address
and control signals for a read operation. The dual-port
retransmits the input clocks relative to the data output. The
buffered clocks are provided on the CQ1, CQ1, CQ0, and CQ0
outputs. Each port has two pairs of Echo clocks. Each clock is
associated with half the data bits. The output clock will match
the corresponding ports I/O configuration.
To enable Echo clock outputs, tie CQEN HIGH. To disable
Echo clock outputs, tie CQEN LOW.
Deterministic Access Control
Deterministic Access Control is provided for ease of design.
The circuitry detects when both ports are accessing the same
location and provides an external BUSY flag to the port on
which data may be corrupted. The collision detection logic
saves the address in conflict (Busy Address) to a readable
register. In the case of multiple collisions, the first Busy
address will be written to the Busy Address register.
If both ports are accessing the same location at the same time
and only one port is doing a write, if tCCS is met, then the data
being written to and read from the address is valid data. For
example, if the right port is reading and the left port is writing
and the left ports clock meets tCCS, then the data being read
from the address by the right port will be the old data. In the
same case, if the right ports clock meets tCCS, then the data
being read out of the address from the right port will be the new
data. In the above case, if tCCS is violated by the either ports
clock with respect to the other port and the right port gets the
external BUSY flag, the data from the right port is corrupted.
the data.
Table 5 shows that in the case of the left port writing and the
right port reading, when an external BUSY flag is asserted on
the right port, the data read out of the device will not be
guaranteed.
The value in the busy address register can be read back to the
address lines. The required input control signals for this
function are shown in Table 8. The value in the busy address
register will be read out to the address lines tCA after the same
amount of latency as a data read operation in SDR mode. In
DDR mode, the address latency is only 2 cycles instead of 2.5
which is the data latency. After an initial address match, the
address under contention is saved in the busy address
register. All following address matches cause the BUSY flag
to be generated, however, none of the addresses are saved
into the busy address register. Once a busy readback is
performed, the address of the first match which happens at
least two clock cycles after the busy readback is saved into the
busy address register.
Figure 2. SDR Echo Clock Delay
Figure 3. DDR Echo Clock Delay
Input Clock
Echo Clock
Data Out
Echo Clock
Input Clock
Data Out
Input Clock
Echo Clock
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| CYDD04S18V18-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 128Kx36 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S18V18-167BBXI | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 128Kx36 90nm DDR IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S18V18-200BBXC | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 128Kx36 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S36V18-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 64Kx72 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD04S36V18-167BBXI | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 64Kx72 90nm DDR IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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