參數(shù)資料
型號： CYD18S72V
廠商： Cypress Semiconductor Corp.
英文描述： FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM)
中文描述： FLEx72 3.3 64K/128K/256K × 72同步雙口RAM（FLEx72 3.3 64K/128K/256K × 72同步雙端口RAM）的
文件頁數(shù)： 25/25頁
文件大?。?/td> 677K
代理商： CYD18S72V
Document #: 38-06069 Rev. *I
Page 25 of 25
CYD04S72V
CYD09S72V
CYD18S72V
Document History Page
Document Title: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
Document Number: 38-06069
Orig. of
Change
**
125859
06/17/03
SPN
*A
128707
08/01/03
SPN
REV.
ECN NO.
Issue Date
Description of Change
New Data Sheet
Added -133 speed bin
Updated spec values for I
CC,
t
HA,
t
HB,
t
HW,
t
HD
Added new parameter I
CC1
Added bank select read and read to write to read (OE=low) timing diagrams
Updated spec values for t
OE,
t
OHZ,
t
CH2,
t
CL2,
t
HA,
t
HB,
t
HW,
t
HD,
I
CC,
I
SB5,
t
SA,
t
SB,
t
SW,
t
SD,
t
CD2
Updated read to write (OE=low) timing diagram
Updated Master Reset values for t
RS,
t
RSR,
t
RSF
Updated pinout
Updated V
CORE
voltage range
Updated package diagram
Updated t
CD2
value on first page
Removed Preliminary status
Added 4 Mbit and 9 Mbit x72 devices into the data sheet with updated pinout,
pin description table, power table, and timing table
Changed title
Added Preliminary status to reflect the addition of 4 Mbit and 9 Mbit devices
Removed FLEx72-E from the document
Added counter related functions for 4 Mbit and 9 Mbit
Removed standard JTAG description
Updated block diagram
Updated pinout with FTSEL and one more PORTSTD pins per port
Updated tRSF of CYD18S72V value
Change pinout D15 from REV[2,4] to VSS to reflect SC pin removal
Changed pinout K3 from NC to NC[2,5]
Changed pinout K20 from NC to NC[2,5]
Changed pinout D15 from VSS to NC
Changed pinout D8 and M3 from REVL[2,4] to VSS
Changed pinout M20 and W15 from REVR[2,4] to VSS
VREF Pin Definition Updated
Added Pb-Free Part Ordering Informations
Added note for V
CORE
Changed notes for PORTSTD to VSS
Changed ICC, ISB1, ISB2 and ISB4 number for CYD09S72V per PE request
Changed CYDxxS72AV to CYDxxS72V (rev. A not implemented)
*B
128997
09/18/03
SPN
*C
129936
09/30/03
SPN
*D
233830
See ECN
WWZ
*E
*F
288892
327355
See ECN
See ECN
WWZ
AEQ
*G
345735
See ECN
PCX
*H
360316
See ECN
YDT
*I
460454
See ECN
YDT
相關(guān)PDF資料
PDF描述
CYD09S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM)
CYDC128B08-55AXC 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B08 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B08-40AXC 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B08-55AXC 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYD18S72V-100BBC 功能描述:靜態(tài)隨機存取存儲器 18M (256Kx72) 3.3v 100MHz Synch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CYD18S72V-100BBI 功能描述:靜態(tài)隨機存取存儲器 18M (256Kx72) 3.3v 100MHz Synch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CYD18S72V-100BBXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-100BBXI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-133BBC 功能描述:靜態(tài)隨機存取存儲器 18M Sync Dual Port 256K x 72 3.3V COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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