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參數(shù)資料
| 型號： | CYD09S72V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM) |
| 中文描述： | FLEx72 3.3 64K/128K/256K × 72同步雙口RAM（FLEx72 3.3 64K/128K/256K × 72同步雙端口RAM）的 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 677K |
| 代理商： | CYD09S72V |
FLEx72 3.3V 64K/128K/256K x 72
Synchronous Dual-Port RAM
Cypress Semiconductor Corporation
Document #: 38-06069 Rev. *I
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 2, 2006
CYD04S72V
CYD09S72V
CYD18S72V
Features
True dual-ported memory cells that allow simultaneous
access of the same memory location
Synchronous pipelined operation
Family of 4-Mbit, 9-Mbit, and 18-Mbit devices
Pipelined output mode allows fast operation
0.18-micron CMOS for optimum speed and power
High-speed clock to data access
3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
484-ball FBGA (1-mm pitch)
Pb-Free packaging available
Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual Chip Enables on both ports for easy depth
expansion
Seamless Migration to Next Generation Dual-Port
Family
Functional Description
The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit
pipelined, synchronous, true dual-port static RAMs that are
high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location
in memory. The result of writing to the same location by more
than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal set-up and
hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S72V device have limited features. Please see
“Address Counter and Mask Register Operations
[17]
” on
page 6“ for details.
Seamless Migration to Next-Generation Dual-Port Family
Cypress offers a migration path for all devices to the
next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details.
Table 1. Product Selection Guide
Density
4-Mbit
(64K x 72)
CYD04S72V
167
4.0
225
484-ball FBGA
23 mm x 23 mm
9-Mbit
(128K x 72)
CYD09S72V
167
4.0
270
484-ball FBGA
23 mm x 23 mm
18-Mbit
(256K x 72)
CYD18S72V
133
5.0
410
484-ball FBGA
23 mm x 23 mm
Part Number
Max. Speed (MHz)
Max. Access Time—Clock to Data (ns)
Typical operating current (mA)
Package
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PDF描述 |
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| CYDC128B08-55AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
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| CYDC064B08-40AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-55AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-55AXI | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYD09S72V-133BBC | 功能描述:靜態(tài)隨機存取存儲器 128K x 72 3.3V COM Sync Dual Port RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD09S72V-133BBI | 功能描述:靜態(tài)隨機存取存儲器 128K x 72 3.3V IND Sync Dual Port RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD09S72V-167BBC | 功能描述:靜態(tài)隨機存取存儲器 128K x 72 3.3V COM Sync Dual Port RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD09S72V18-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 9216K (128Kx72) 1.8v 167MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD09S72V18-167BBXI | 功能描述:IC SRAM 9MBIT 167MHZ 256LFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
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