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參數(shù)資料
| 型號： | CYD09S72V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM) |
| 中文描述： | FLEx72 3.3 64K/128K/256K × 72同步雙口RAM（FLEx72 3.3 64K/128K/256K × 72同步雙端口RAM）的 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 677K |
| 代理商： | CYD09S72V |
Document #: 38-06069 Rev. *I
Page 4 of 25
CYD04S72V
CYD09S72V
CYD18S72V
Pin Definitions
Left Port
Right Port
Description
A
0L
–A
17L
A
0R
–A
17R
Address Inputs
.
BE
0L
–BE
7L
BE
0R
–BE
7R
Byte Enable Inputs
. Asserting these signals enables Read and Write operations
to the corresponding bytes of the memory array.
BUSY
L[2,5]
BUSY
R[2,5]
Port Busy Output
.
When the collision is detected, a BUSY is asserted.
C
L
C
R
Input Clock Signal
.
CE0
L[9]
CE0
R[9]
Active Low Chip Enable Input
.
CE1
L[8]
CE1
R[8]
Active High Chip Enable Input
.
DQ
0L
–DQ
71L
DQ
0R
–DQ
71R
Data Bus Input/Output
.
OE
L
OE
R
Output Enable Input
. This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
INT
L
INT
R
Mailbox Interrupt Flag Output
.
The mailbox permits communications between
ports. The upper two memory locations can be used for message passing. INT
L
is
asserted LOW when the right port writes to the mailbox location of the left port, and
vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of
its mailbox.
LowSPD
L[2,4]
LowSPD
R[2,4]
Port Low Speed Select Input
.
When operating at less than 100 MHz, the LowSPD
disables the port DLL.
PORTSTD[1:0]
L[2,4]
PORTSTD[1:0]
R[2,4]
Port Address/Control/Data I/O Standard Select Input
.
R/W
L
R/W
R
Read/Write Enable Input
. Assert this pin LOW to write to, or HIGH to Read from
the dual-port memory array.
READY
L[2,5]
READY
R[2,5]
Port Ready Output
.
operation.
CNT/MSK
L[8]
CNT/MSK
R[8]
Port Counter/Mask Select Input
.
Counter control input.
ADS
L[9]
ADS
R[9]
Port Counter Address Load Strobe Input
.
Counter control input.
CNTEN
L[9]
CNTEN
R[9]
Port Counter Enable Input
.
Counter control input.
CNTRST
L[8]
CNTRST
R[8]
Port Counter Reset Input
. Counter control input.
CNTINT
L[10]
CNTINT
R[10]
Port Counter Interrupt Output
. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
WRP
L[2,3]
WRP
R[2,3]
Port Counter Wrap Input
.
After the burst counter reaches the maximum count, if
WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be
loaded with the value stored in the mirror register.
RET
L[2,3]
RET
R[2,3]
Port Counter Retransmit Input
.
Counter control input.
FTSEL
L[2,3]
FTSEL
R[2,3]
Flow-Through Select
. Use this pin to select Flow-Through mode. When is
de-asserted, the device is in pipelined mode.
VREF
L[2,4]
VREF
R[2,4]
Port External High-Speed IO Reference Input
.
VDDIO
L
VDDIO
R
Port IO Power Supply
.
REV
[2,4]L
REV
[2,4]R
Reserved pins for future features
.
MRST
Master Reset Input
. MRST is an asynchronous input signal and affects both ports.
A master reset operation is required at power-up.
TRST
[2,5]
JTAG Reset Input
.
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