參數(shù)資料
型號(hào)： CYD09S72V
廠商： Cypress Semiconductor Corp.
英文描述： FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM)
中文描述： FLEx72 3.3 64K/128K/256K × 72同步雙口RAM（FLEx72 3.3 64K/128K/256K × 72同步雙端口RAM）的
文件頁(yè)數(shù)： 5/25頁(yè)
文件大?。?/td> 677K
代理商： CYD09S72V
Document #: 38-06069 Rev. *I
Page 5 of 25
CYD04S72V
CYD09S72V
CYD18S72V
Master Reset
The FLEx72 family devices undergo a complete reset by
taking the MRST input LOW. MRST input can switch
asynchronously to the clocks. MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the mailbox
interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx72 family
devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports.
Table 2
shows the interrupt operation for both ports using 18 Mbit
device as an example. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for
the left port.
Table 2.
shows that in order to set the INT
R
flag, a
Table 2. Interrupt Operation Example
[1, 12, 13, 14]
write operation by the left port to address 3FFFF will assert
INT
R
LOW. At least one byte has to be active for a write to
generate an interrupt. A valid Read of the 3FFFF location by
the right port will reset INT
R
HIGH. At least one byte has to be
active in order for a read to reset the interrupt. When one port
writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port)
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
TMS
JTAG Test Mode Select Input
. It controls the advance of JTAG TAP state
machine. State machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input
. Data on the TDI input will be shifted serially into selected
registers.
TCK
JTAG Test Clock Input
.
TDO
JTAG Test Data Output
. TDO transitions occur on the falling edge of TCK. TDO
is normally three-stated except when captured data is shifted out of the JTAG TAP.
V
SS
Ground Inputs
.
V
CORE[11]
Core Power Supply
.
V
TTL
LVTTL Power Supply
.
Pin Definitions
(continued)
Left Port
Right Port
Description
Function
Left Port
Right Port
R/W
L
L
CE
L
L
A
0
L
–17
L
3FFFF
INT
L
X
R/W
R
X
CE
R
X
A
0R–17R
X
INT
R
L
Set Right INT
R
Flag
Reset Right INT
R
Flag
X
X
X
X
H
L
3FFFF
H
Set Left INT
L
Flag
X
X
X
L
L
L
3FFFE
X
Reset Left INT
L
Flag
H
L
3FFFE
H
X
X
X
X
Notes:
11. This family of Dual-Ports does not use V
, and these pins are internally NC. The next generation Dual-Port family, the FLEx72-E, will use V
CORE
of 1.5V
or 1.8V. Please contact local Cypress FAE for more information.
12.CE is internal signal. CE = LOW if CE
= LOW and CE
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
13.OE is “Don’t Care” for mailbox operation.
14.At least one of BE0 or BE7 must be LOW.
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