參數(shù)資料
型號(hào): CYD18S72V
廠商: Cypress Semiconductor Corp.
英文描述: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM)
中文描述: FLEx72 3.3 64K/128K/256K × 72同步雙口RAM(FLEx72 3.3 64K/128K/256K × 72同步雙端口RAM)的
文件頁(yè)數(shù): 22/25頁(yè)
文件大?。?/td> 677K
代理商: CYD18S72V
Document #: 38-06069 Rev. *I
Page 22 of 25
CYD04S72V
CYD09S72V
CYD18S72V
Counter Interrupt and Retransmit
[48, 49, 50, 51, 52]
Mailbox Interrupt Timing
[53, 54, 55, 56, 57]
Notes:
48.CE
= OE = BE0 – BE7 = LOW; CE
1
= R/W = CNTRST = MRST = HIGH.
49.CNTINT is always driven.
50.CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
51.The mask register assumed to have the value of 1FFFFh.
52.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
53.CE
= OE = ADS = CNTEN = LOW; CE
= CNTRST = MRST = CNT/MSK = HIGH.
54.Address “1FFFF” is the mailbox location for R_Port.
55.L_Port is configured for Write operation, and R_Port is configured for Read operation.
56.At least one byte enable (B0 – B3) is required to be active during interrupt operations.
57.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
Switching Waveforms
(continued)
t
CH2
t
CL2
t
CYC2
CLK
1FFFD
1FFFF
INTERNAL
ADDRESS
Last_Loaded
Last_Loaded +1
t
HCM
COUNTER
1FFFE
CNTINT
t
SCINT
t
RCINT
1FFFC
CNTEN
ADS
CNT/MSK
t
SCM
t
CH2
t
CL2
t
CYC2
CLK
L
t
CH2
t
CL2
t
CYC2
CLK
R
3FFFF
t
SA
t
HA
A
n+3
A
n
A
n+1
A
n+2
L_PORT
ADDRESS
A
m
A
m+4
A
m+1
3FFFF
A
m+3
R_PORT
ADDRESS
INT
R
t
SA
t
HA
t
SINT
t
RINT
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