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參數(shù)資料
| 型號(hào)： | CYD18S72V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM) |
| 中文描述： | FLEx72 3.3 64K/128K/256K × 72同步雙口RAM（FLEx72 3.3 64K/128K/256K × 72同步雙端口RAM）的 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 677K |
| 代理商： | CYD18S72V |
Document #: 38-06069 Rev. *I
Page 13 of 25
CYD04S72V
CYD09S72V
CYD18S72V
t
HAD
t
SCN
t
HCN
t
SRST
t
HRST
t
SCM
t
HCM
t
OE
t
OLZ[27, 28]
t
OHZ[27, 28]
t
CD2
t
CA2
t
CM2
ADS Hold Time
0.6
0.6
NA
NA
ns
CNTEN Set-up Time
2.3
2.5
NA
NA
ns
CNTEN Hold Time
0.6
0.6
NA
NA
ns
CNTRST Set-up Time
2.3
2.5
NA
NA
ns
CNTRST Hold Time
0.6
0.6
NA
NA
ns
CNT/MSK Set-up Time
2.3
2.5
NA
NA
ns
ns
ns
CNT/MSK Hold Time
0.6
0.6
NA
NA
Output Enable to Data Valid
4.0
4.4
5.5
5.5
OE to Low Z
0
0
0
0
ns
OE to High Z
0
4.0
0
4.4
0
5.5
0
5.5
ns
Clock to Data Valid
4.0
4.4
5.0
5.2
ns
Clock to Counter Address Valid
4.0
4.4
NA
NA
ns
Clock to Mask Register
Readback Valid
4.0
4.4
NA
NA
ns
t
DC
Data Output Hold After Clock
HIGH
1.0
1.0
1.0
1.0
ns
t
CKHZ[27, 28]
t
CKLZ[27, 28]
t
SINT
t
RINT
t
SCINT
t
RCINT
Port to Port Delays
Clock HIGH to Output High Z
0
4.0
0
4.4
0
4.7
0
5.0
ns
Clock HIGH to Output Low Z
1.0
4.0
1.0
4.4
1.0
4.7
1.0
5.0
ns
Clock to INT Set Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10
ns
Clock to INT Reset Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10
ns
Clock to CNTINT Set Time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
Clock to CNTINT Reset time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
t
CCS
Master Reset Timing
Clock to Clock Skew
5.2
6.0
5.7
8.0
ns
t
RS
t
RSS
t
RSR
t
RSF
t
RSCNTINT
Master Reset Pulse Width
5.0
5.0
5.0
5.0
cycles
Master Reset Set-up Time
6.0
6.0
6.0
8.5
ns
Master Reset Recovery Time
5.0
5.0
5.0
5.0
cycles
Master Reset to Outputs Inactive
10.0
10.0
10.0
10.0
ns
Master Reset to Counter
Interrupt Flag Reset Time
10.0
10.0
NA
NA
ns
Notes:
27.This parameter is guaranteed by design, but is not production tested.
28.Test conditions used are Load 2.
Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
–167
–133
–100
Unit
CYD04S72V
CYD09S72V
CYD04S72V
CYD09S72V
CYD18S72V
CYD18S72V
Min.
Max
Min.
Max
Min.
Max
Min.
Max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYD09S72V | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM) |
| CYDC128B08-55AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08 | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-40AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-55AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYD18S72V-100BBC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18M (256Kx72) 3.3v 100MHz Synch 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD18S72V-100BBI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18M (256Kx72) 3.3v 100MHz Synch 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD18S72V-100BBXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| CYD18S72V-100BBXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| CYD18S72V-133BBC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18M Sync Dual Port 256K x 72 3.3V COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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