- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378513 > CY7C9689-AI (CYPRESS SEMICONDUCTOR CORP) TAXI Compatible HOTLink Transceiver PDF資料下載
參數(shù)資料
| 型號： | CY7C9689-AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TAXI Compatible HOTLink Transceiver |
| 中文描述： | 1 CHANNEL(S), 200M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大小： | 1009K |
| 代理商： | CY7C9689-AI |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
CY7C9689
5
18
TXEN
TTL input, sampled on
TXCLK
|
or REFCLK
|
Internal Pull-Up
Transmit Enable.
TXEN is sampled on the rising edge of the TXCLK or REFCLK input and enables
parallel data bus write operations (when selected). The device is selected when
TXEN is asserted during a clock cycle immediately following one in which CE
is sampled LOW.
Depending on the level on EXTFIFO, the asserted state for TXEN can be active
HIGH or active LOW. If EXTFIFO is LOW, then TXEN is active LOW and data
is captured on the same clock cycle where TXEN is sampled LOW. If EXTFIFO
is HIGH, then TXEN is active HIGH and data is captured on the clock cycle
following any clock edge when TXEN is sampled HIGH.
Transmitter BIST Enable.
When TXBISTEN is LOW, the transmitter generates a 511-character repeating
sequence that can be used to validate link integrity. This 4B/5B BIST sequence
is generated regardless of the state of other configuration inputs. The transmit-
ter returns to normal operation when TXBISTEN is HIGH. All Transmit FIFO
read operations are suspended when BIST is active.
Reset Transmit FIFO.
When the Transmit FIFO is enabled (FIFOBYP is HIGH), TXEN is deasserted,
CE is asserted (LOW), and TXRST is sampled LOW by TXCLK for seven cycles,
the Transmit FIFO begins its internal reset process. The Transmit FIFO TXFULL
flag is asserted and the host interface counter and address pointer are zeroed.
This reset propagates to the serial transmit side, any remaining counters and
pointers. The TXFULL flag is asserted until both sides of the Transmit FIFO have
reset. While TXRST remains asserted, the Transmit FIFO remains in reset and
the TXFULL output remains asserted.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored.
Transmitter Halt Control Input.
When TXHALT is asserted LOW, transmission of data is suspended and the
HOTLink TAXI transmits SYNC characters. When TXHALT is deasserted HIGH,
normal data processing proceeds.
If the Transmit FIFO is enabled (FIFOBYP is HIGH), the interface is allowed to
continue loading data into the Transmit FIFO while TXHALT is asserted.
Transmit FIFO Full Status Flag.
When the Transmit FIFO is enabled (FIFOBYP is HIGH) and its flags are driven
(CE is LOW), TXFULL is asserted when four or fewer characters can be written
to the HOTLink Transmit FIFO. If a Transmit FIFO reset has been initiated
(TXRST was sampled asserted for a minimum of seven TXCLK cycles),
TXFULL is asserted to enforce the full/unavailable status of the Transmit FIFO
during reset.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), the TXFULL output
changes after the rising edge of REFCLK. TXFULL is asserted when the trans-
mitter is BUSY (not accepting a new data or command characters) and deas-
serted when new characters can be accepted.
When the Transmit FIFO is bypassed and RANGESEL is HIGH or SPDSEL is
LOW, TXFULL toggles at the character rate to provide a character rate reference
control-indication since REFCLK is operating at twice of the data rate.
The asserted state of this output (HIGH or LOW) is determined by the state of
the EXTFIFO input. When EXTFIFO is LOW, TXFULL is active LOW. When
EXTFIFO is HIGH, TXFULL is active HIGH.
7
TXBISTEN
TTL input,
asynchronous
Internal Pull-Up
16
TXRST
TTL input, sampled on
TXCLK
|
Internal Pull-Up
9
TXHALT
TTL input, sampled on
TXCLK
|
Internal Pull-Up
72
TXFULL
Three-state TTL out-
put, changes following
TXCLK
|
or REFCLK
|
Pin Descriptions
(continued)
Pin
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY8C21323 | PSoC Mixed-Signal Array(PSoC混合信號陣列) |
| CY8C21123 | PSoC Mixed-Signal Array(PSoC混合信號陣列) |
| CY8C21223 | PSoC Mixed-Signal Array(PSoC混合信號陣列) |
| CY8C21634-24AX | PSoC Mixed-Signal Array |
| CY8C21534 | PSoC Mixed-Signal Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C9915JXC-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C9915JXI-1 | 功能描述:IC CLK BUFF SKEW 8OUT 32PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:RoboClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY7C9915JXI-1T | 功能描述:IC CLK BUFF SKEW 8OUT 32PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:RoboClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY7C9915JXI-5 | 制造商:Cypress Semiconductor 功能描述: |
| CY7CD68321C-56LFXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。