參數(shù)資料
型號(hào)： CY7C9689-AI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： TAXI Compatible HOTLink Transceiver
中文描述： 1 CHANNEL(S), 200M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 26/48頁(yè)
文件大?。?/td> 1009K
代理商： CY7C9689-AI
CY7C9689
26
CY7C9689 Receiver Switching Characteristics
Over the Operating Range
Parameter
t
B[23]
t
SA
t
EFW
t
IN_J
Description
Min.
Max.
Unit
Bit Time
Static Alignment
[16, 24]
Error Free Window
[16, 25, 26]
IN± Peak-to-Peak Input Jitter Tolerance
[16, 25, 27, 30]
20.0
5.0
ns
600
ps
0.65
UI
0.5
UI
CY7C9689 Transmitter Switching Characteristics
Over the Operating Range
Parameter
t
B[23]
t
RISE
t
FALL
t
DJ
t
RJ
t
JT
Description
Min.
Max.
Unit
Bit Time
PECL Output Rise Time 20
80% (PECL Test Load)
[16]
PECL Output Fall Time 80
20% (PECL Test Load)
[16]
Deterministic Jitter (peak-peak)
[16, 28]
Random Jitter (
σ
)
[16, 29]
Transmitter Total Output Jitter (peak-peak)
[16]
20.0
5.0
ns
200
1700
ps
200
1700
ps
0.02
UI
0.008
UI
0.08
UI
Notes:
23. The PECL switching threshold is the midpoint between the PECL
V
, and V
specification (approximately V
1.33V).
24. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by the absolute difference
of the left and right edge shifts (|t
–
t
|) of one bit until a character error occurs.
25. Receiver UI (Unit Interval) is calculated as 1/(f
*N) when operated in 8-bit mode (N=10) and 10-bit mode (N=12) if no data is being received, or 1/(f
*N)
of the remote transmitter if data is being received. In an operating link this is equivalent to N * t
when REFCLK = 1X the character rate. An alternate multiply
ratios (2X or 4X, as selected by SPDSEL and RANGESEL), the numerator is multiplied by 2 or 4 respectively.
26. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter
<
50% Dj.
27. The specification is sum of 25% Duty Cycle Distortion (DCD), 10% Data Dependant Jitter (DDJ), 15% Random Jitter (RJ).
28. While sending continuous JK, outputs loaded to 50
to V
1.3V, over the operating range.
29. While sending continuous HH, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating
range
30. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
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