- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379096 > CY7C63743C (Cypress Semiconductor Corp.) enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) PDF資料下載
參數(shù)資料
| 型號： | CY7C63743C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) |
| 中文描述： | 的enCoRe USB的組合低速USB和PS / 2外設(shè)控制器（的enCoRe的USB結(jié)合低速的USB和的PS / 2外設(shè)控制器） |
| 文件頁數(shù)： | 27/49頁 |
| 文件大?。?/td> | 1942K |
| 代理商： | CY7C63743C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 27 of 49
20.0
Processor Status and Control Register
Bit 7: IRQ Pending
When an interrupt is generated, it is registered as a pending
interrupt. The interrupt will remain pending until its interrupt
enable bit is set (
Figure 21-1
and
Figure 21-2
) and inter-
rupts are globally enabled (Bit 2, Processor Status and
Control Register). At that point the internal interrupt han-
dling sequence will clear the IRQ Pending bit until another
interrupt is detected as pending. This bit is only valid if the
Global Interrupt Enable bit is disabled.
1 = There are pending interrupts.
0 = No pending interrupts.
Bit 6: Watchdog Reset
The Watchdog Timer Reset (WDR) occurs when the inter-
nal Watchdog timer rolls over. The timer will roll over and
WDR will occur if it is not cleared within t
WATCH
(see Section
26.0 for the value of t
WATCH
). This bit is cleared by an
LVR/BOR. Note that a Watchdog reset can occur with a
POR/LVR/BOR event, as discussed at the end of this sec-
tion.
1 = A Watchdog reset occurs.
0 = No Watchdog reset
Bit 5: Bus Interrupt Event
The Bus Reset Status is set whenever the event for the
USB Bus Reset or PS/2 Activity interrupt occurs. The event
type (USB or PS/2) is selected by the state of the USB-PS/2
Interrupt Mode bit in the USB Status and Control Register
(see
Figure 13-1
). The details on the event conditions that
set this bit are given in Section 21.3. In either mode, this bit
is set as soon as the event has lasted for 128–256
μ
s, and
the bit will be set even if the interrupt is not enabled. The bit
is only cleared by firmware or LVR/WDR.
1 = A USB reset occurred or PS/2 Activity is detected, de-
pending on USB-PS/2 Interrupt Select bit.
0 = No event detected since last cleared by firmware or
LVR/WDR.
Bit 4: LVR/BOR Reset
The Low-voltage or Brown-out Reset is set to ‘1’ during a
power-on reset. Firmware can check bits 4 and 6 in the
reset handler to determine whether a reset was caused by
a LVR/BOR condition or a Watchdog timeout. This bit is not
affected by WDR. Note that a LVR/BOR event may be fol-
lowed by a Watchdog reset before firmware begins execut-
ing, as explained at the end of this section.
1 = A POR or LVR has occurred.
0 = No POR nor LVR since this bit last cleared.
Bit 3: Suspend
Writing a '1' to the Suspend bit will halt the processor and
cause the microcontroller to enter the suspend mode that
significantly reduces power consumption. An interrupt or
USB bus activity will cause the device to come out of sus-
pend. After coming out of suspend, the device will resume
firmware execution at the instruction following the IOWR
which put the part into suspend. When writing the suspend
bit with a resume condition present (such as non-idle USB
activity), the suspend state will still be entered, followed
immediately by the wake-up process (with appropriate de-
lays for the clock start-up). See Section 11.0 for more de-
tails on suspend mode operation.
1 = Suspend the processor.
0 = Not in suspend mode. Cleared by the hardware when
resuming from suspend.
Bit 2: Interrupt Enable Sense
This bit shows whether interrupts are enabled or disabled.
Firmware has no direct control over this bit as writing a zero
or one to this bit position will have no effect on interrupts.
This bit is further gated with the bit settings of the Global
Interrupt Enable Register (
Figure 21-1
) and USB Endpoint
Interrupt Enable Register (
Figure 21-2
). Instructions DI, EI,
and RETI manipulate the state of this bit.
1 = Interrupts are enabled.
0 = Interrupts are masked off.
Bit 1:
Reserved. Must be written as a 0.
Bit 0: Run
This bit is manipulated by the HALT instruction. When Halt
is executed, the processor clears the run bit and halts at the
end of the current instruction. The processor remains halt-
ed until a reset occurs (low-voltage, brown-out, or Watch-
dog). This bit should normally be written as a ‘1’.
During power-up, or during a low-voltage reset, the Processor
Status and Control Register is set to 00010001, which
indicates a LVR/BOR (bit 4 set) has occurred and no interrupts
are pending (bit 7 clear). Note that during the t
START
ms partial
suspend at start-up (explained in Section 10.1), a Watchdog
Reset will also occur. When a WDR occurs during the
power-up suspend interval, firmware would read 01010001
from the Status and Control Register after power-up. Normally
the LVR/BOR bit should be cleared so that a subsequent WDR
can be clearly identified.
Note that if a USB bus reset (long
SE0) is received before firmware examines this register, the
Bus Interrupt Event bit would also be set.
Bit #
7
6
5
4
3
2
1
0
Bit Name
IRQ
Pending
Watchdog
Reset
Bus
Interrupt
Event
LVR/BOR
Reset
Suspend
Interrupt
Enable
Sense
Reserved
Run
Read/Write
R
R/W
R/W
R/W
R/W
R
-
R/W
Reset
0
1
0
1
0
0
0
1
Figure 20-1. Processor Status and Control Register (Address 0xFF)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C63723C | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) |
| CY7C63803 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| CY7C63310 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| CY7C63801 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| CY7C63823 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXCT | 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743-PC | 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。