參數(shù)資料
型號： CY7C63743C
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
中文描述： 的enCoRe USB的組合低速USB和PS / 2外設(shè)控制器（的enCoRe的USB結(jié)合低速的USB和的PS / 2外設(shè)控制器）
文件頁數(shù)： 21/49頁
文件大小： 1942K
代理商： CY7C63743C
CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 21 of 49
17.0
Serial Peripheral Interface (SPI)
SPI is a four-wire, full-duplex serial communication interface
between a master device and one or more slave devices. The
CY7C637xxC SPI circuit supports byte serial transfers in
either Master or Slave modes. The block diagram of the SPI
circuit is shown in
Figure 17-1
. The block contains buffers for
both transmit and receive data for maximum flexibility and
throughput. The CY7C637xxC can be configured as either an
SPI Master or Slave. The external interface consists of
Master-Out/Slave-In (MOSI), Master-In/Slave-Out (MISO),
Serial Clock (SCK), and Slave Select (SS).
SPI modes are activated by setting the appropriate bits in the
SPI Control Register, as described below.
The SPI Data Register below serves as a transmit and receive
buffer.
Bit [7:0]: Data I/O[7:0]
Writes to the SPI Data Register load the transmit buffer,
while reads from this register read the receive buffer con-
tents.
1 = Logic HIGH
0 = Logic LOW
17.1
Only an SPI Master can initiate a byte/data transfer. This is
done by the Master writing to the SPI Data Register. The
Master shifts out 8 bits of data (MSB first) along with the serial
clock SCK for the Slave. The Master’s outgoing byte is
replaced with an incoming one from a Slave device. When the
last bit is received, the shift register contents are transferred
to the receive buffer and an interrupt is generated. The receive
data must be read from the SPI Data Register before the next
byte of data is transferred to the receive buffer, or the data will
be lost.
Operation as an SPI Master
When operating as a Master, an active LOW Slave Select (SS)
must be generated to enable a Slave for a byte transfer. This
Slave Select is generated under firmware control, and is not
part of the SPI internal hardware. Any available GPIO can be
used for the Master’s Slave Select output.
When the Master writes to the SPI Data Register, the data is
loaded into the transmit buffer. If the shift register is not busy
shifting a previous byte, the TX buffer contents will be automat-
ically transferred into the shift register and shifting will begin.
If the shift register is busy, the new byte will be loaded into the
shift register only after the active byte has finished and is trans-
ferred to the receive buffer. The new byte will then be shifted
out. The Transmit Buffer Full (TBF) bit will be set HIGH until
the transmit buffer’s data-byte is transferred to the shift
register. Writing to the transmit buffer while the TBF bit is HIGH
will overwrite the old byte in the transmit buffer.
The byte shifting and SCK generation are handled by the
hardware (based on firmware selection of the clock source).
Data is shifted out on the MOSI pin (P0.5) and the serial clock
is output on the SCK pin (P0.7). Data is received from the slave
on the MISO pin (P0.6). The output pins must be set to the
desired drive strength, and the GPIO data register must be set
to 1 to enable a bypass mode for these pins. The MISO pin
must be configured in the desired GPIO input mode. See
Section 12.0 for GPIO configuration details.
17.2
The Master’s SCK is programmable to one of four clock
settings, as shown in
Figure 17-1
. The frequency is selected
with the Clock Select Bits of the SPI control register. The
Master SCK Selection
8 bit shift register
Data Bus
Data Bus
MOSI
MISO
SCK
SS
Master
/ Slave
Control
Write
Read
4
TX Buffer
RX Buffer
Internal SCK
Figure 17-1. SPI Block Diagram
Bit #
7
6
5
4
3
2
1
0
Bit Name
Data I/O
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
Figure 17-2. SPI Data Register (Address 0x60)
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CY7C63743C-QXC 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63743C-SXC 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63743C-SXCT 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
CY7C63743-PC 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382
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