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參數(shù)資料
| 型號： | CY7C63743C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) |
| 中文描述： | 的enCoRe USB的組合低速USB和PS / 2外設(shè)控制器（的enCoRe的USB結(jié)合低速的USB和的PS / 2外設(shè)控制器） |
| 文件頁數(shù)： | 22/49頁 |
| 文件大?。?/td> | 1942K |
| 代理商： | CY7C63743C |
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CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 22 of 49
hardware provides 8 output clocks on the SCK pin (P0.7) for
each byte transfer. Clock phase and polarity are selected by
the CPHA and CPOL control bits (see
Figure 17-1
and
17-4
).
The master SCK duty cycle is nominally 33% in the fastest (2
Mbps) mode, and 50% in all other modes.
17.3
In slave mode, the chip receives SCK from an external master
on pin P0.7. Data from the master is shifted in on the MOSI pin
(P0.5), while data is being shifted out of the slave on the MISO
pin (P0.6). In addition, the active LOW Slave Select must be
asserted to enable the slave for transmit. The Slave Select pin
is P0.4. These pins must be configured in appropriate GPIO
modes, with the GPIO data register set to 1 to enable bypass
mode selected for the MISO pin.
In Slave mode, writes to the SPI Data Register load the
Transmit buffer. If the Slave Select is asserted (SS LOW) and
the shift register is not busy shifting a previous byte, the
transmit buffer contents will be automatically transferred into
the shift register. If the shift register is busy, the new byte will
be loaded into the shift register only after the active byte has
finished and is transferred to the receive buffer. The new byte
is then ready to be shifted out (shifting waits for SCK from the
Master). If the Slave Select is not active when the transmit
buffer is loaded, data is not transferred to the shift register until
Slave Select is asserted. The Transmit Buffer Full (TBF) bit will
be set to ‘1’ until the transmit buffer’s data-byte is transferred
to the shift register. Writing to the transmit buffer while the TBF
bit is HIGH will overwrite the old byte in the Transmit Buffer.
If the Slave Select is deasserted before a byte transfer is
complete, the transfer is aborted and no interrupt is generated.
Whenever Slave Select is asserted, the transmit buffer is
automatically reloaded into the shift register.
Clock phase and polarity must be selected to match the SPI
master, using the CPHA and CPOL control bits (see
Figure 17-3
and
Figure 17-4
).
The SPI slave logic continues to operate in suspend, so if the
SPI interrupt is enabled, the device can go into suspend during
a SPI slave transaction, and it will wake up at the interrupt that
signals the end of the byte transfer.
Operation as an SPI Slave
17.4
The SPI Control Register is shown in
Figure 17-3
. The timing
diagram in
Figure 17-4
shows the clock and data states for the
various SPI modes.
SPI Status and Control
Bit 7: TCMP
1 = TCMP is set to 1 by the hardware when 8-bit transfer is
complete. The SPI interrupt is asserted at the same time
TCMP is set to 1.
0 = This bit is only cleared by firmware.
Bit 6: TBF
Transmit Buffer Full bit.
1 = Indicates data in the transmit buffer has not transferred
to the shift register.
0 = Indicates data in the transmit buffer has transferred to
the shift register.
Bit [5:4] Comm Mode[1:0]
00 = All communications functions disabled (default).
01 = SPI Master Mode.
10 = SPI Slave Mode.
11 = Reserved.
Bit 3: CPOL
SPI Clock Polarity bit.
1 = SCK idles HIGH.
0 = SCK idles LOW.
Bit 2: CPHA
SPI Clock Phase bit (see
Figure 17-4
)
Bit [1:0]: SCK Select
Master mode SCK frequency selection (no effect in Slave
Mode):
00 = 2 Mbit/s
01 = 1 Mbit/s
10 = 0.5 Mbit/s
11 = 0.0625 Mbit/s
Bit #
7
6
5
4
3
2
1
0
Bit Name
TCMP TBF
Comm
Mode[1:0]
CPOL CPHA
SCK
Select
Read/Write
R/W
R/W R/W R/W R/W
R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
Figure 17-3. SPI Control Register (Address 0x61)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C63723C | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) |
| CY7C63803 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| CY7C63310 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| CY7C63801 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| CY7C63823 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXCT | 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743-PC | 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
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