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參數資料
| 型號： | CY7C63743C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結合低速USB和PS/2外設控制器) |
| 中文描述： | 的enCoRe USB的組合低速USB和PS / 2外設控制器（的enCoRe的USB結合低速的USB和的PS / 2外設控制器） |
| 文件頁數： | 12/49頁 |
| 文件大?。?/td> | 1942K |
| 代理商： | CY7C63743C |
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CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 12 of 49
The microcontroller begins execution from ROM address
0x0000 after a LVR, BOR, or WDR reset. Although this looks
like interrupt vector 0, there is an important difference. Reset
processing does NOT push the program counter, carry flag,
and zero flag onto program stack. Attempting to execute either
a RET or RETI in the reset handler will cause unpredictable
execution results.
The following events take place on reset. More details on the
various resets are given in the following sections.
1. All registers are reset to their default states (all bits cleared,
except in Processor Status and Control Register).
2. GPIO and USB pins are set to high-impedance state.
3. The VREG pin is set to high-impedance state.
4. Interrupts are disabled.
5. USB operation is disabled and must be enabled by firmware
if desired, as explained in Section 14.1.
6. For a BOR or LVR, the external oscillator is disabled and
Internal Clock mode is activated, followed by a time-out
period t
START
for V
CC
to stabilize. A WDR does not change
the clock mode, and there is no delay for V
CC
stabilization
on a WDR. Note that the External Oscillator Enable (Bit 0,
Figure 9-2
) will be cleared by a WDR, but it does not take
effect until suspend mode is entered.
7. The Program Stack Pointer (PSP) and Data Stack Pointer
(DSP) reset to address 0x00. Firmware should move the
DSP for USB applications, as explained in Section 6.5.
8. Program execution begins at address 0x0000 after the
appropriate time-out period.
10.1
When V
CC
is first applied to the chip, the internal oscillator is
started and the Low-voltage Reset is initially enabled by
default. At the point where V
CC
has risen above V
LVR
(see
Section 25.0 for the value of V
LVR
), an internal counter starts
counting for a period of t
START
(see Section 26.0 for the value
of t
START
). During this t
START
time, the microcontroller enters
a partial suspend state to wait for V
CC
to stabilize before it
begins executing code from address 0x0000.
As long as the LVR circuit is enabled, this reset sequence
repeats whenever the V
CC
pin voltage drops below V
LVR
. The
LVR can be disabled by firmware by setting the Low-voltage
Low-voltage Reset (LVR)
Reset Disable bit in the Clock Configuration Register
(
Figure 9-2
). In addition, the LVR is automatically disabled in
suspend mode to save power. If the LVR was enabled before
entering suspend mode, it becomes active again once the
suspend mode ends.
When LVR is disabled during normal operation (i.e., by writing
‘0’ to the Low-voltage Reset Disable bit in the Clock Configu-
ration Register), the chip may enter an unknown state if V
CC
drops below V
LVR
. Therefore, LVR should be enabled at all
times during normal operation. If LVR is disabled (i.e., by
firmware or during suspend mode), a secondary low-voltage
monitor, BOR, becomes active, as described in the next
section. The LVR/BOR Reset bit of the Processor Status and
Control Register (
Figure 20-1
), is set to ‘1’ if either a LVR or
BOR has occurred.
10.2
The Brown Out Reset (BOR) circuit is always active and
behaves like the POR. BOR is asserted whenever the V
CC
voltage to the device is below an internally defined trip voltage
of approximately 2.5V. The BOR re-enables LVR. That is, once
V
CC
drops and trips BOR, the part remains in reset until V
CC
rises above V
LVR
. At that point, the t
START
delay occurs before
normal operation resumes, and the microcontroller starts
executing code from address 0x00 after the t
START
delay.
In suspend mode, only the BOR detection is active, giving a
reset if V
CC
drops below approximately 2.5V. Since the device
is suspended and code is not executing, this lower reset
voltage is safe for retaining the state of all registers and
memory. Note that in suspend mode, LVR is disabled as
discussed in Section 10.1.
Brown Out Reset (BOR)
10.3
The Watchdog Timer Reset (WDR) occurs when the internal
Watchdog timer rolls over. Writing any value to the write-only
Watchdog Reset Register at address 0x26 will clear the timer.
The timer will roll over and WDR will occur if it is not cleared
within t
WATCH
(see
Figure 10-1
) of the last clear. Bit 6
(Watchdog Reset bit) of the Processor Status and Control
Register is set to record this event (see Section 20.0 for more
details). A Watchdog Timer Reset typically lasts for 2–4 ms,
after which the microcontroller begins execution at ROM
address 0x0000.
Watchdog Reset (WDR)
At least 10.1 ms
since last write to WDR
WDR goes HIGH
for 2–4 ms
Execution begins at
ROM Address 0x0000
2–4 ms
14.6 ms
(at F
OSC
= 6 MHz)
WDR
t
WATCH = 10.1 to
Figure 10-1. Watchdog Reset (WDR, Address 0x26)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXCT | 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743-PC | 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應用 系列:enCoRe™ 產品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應用:網絡處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網，UART，USB 輸入/輸出數:- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應商設備封裝:PG-LQFP-208 其它名稱:SP000314382 |
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