參數(shù)資料
型號(hào)： CY7C60223
廠商： Cypress Semiconductor Corp.
英文描述： Wireless enCoRe II Microcontroller(無(wú)線enCoRe II微控制器)
中文描述： 的Wireless enCoRe II微控制器（無(wú)線enCoRe II還微控制器）
文件頁(yè)數(shù)： 46/62頁(yè)
文件大?。?/td> 1276K
代理商： CY7C60223
CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 46 of 62
‘
Programmable Interval Timer
Table 74.Timer Capture 1 Falling (TCAP1F) [0x25] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Capture 1 Falling [7:0]
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Capture 1 Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TCAP1 input. The bits that
are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When capture 0 is in 16-bit mode this
register holds the high-order 8 bits of the 16-bit timer from the last Capture 0 falling edge. When Capture 0 is in 16-bit mode this
register will be loaded with high-order 8 bits of the 16-bit timer on TCAP0 falling edge.
Table 75.Capture Interrupt Status (TCAPINTS) [0x2C] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Cap1 Fall
Active
Cap1 Rise
Active
Cap0 Fall
Active
Cap0 Rise
Active
Read/Write
–
–
–
–
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
These four bits contains the status bits for the four timer captures for the four timer block capture interrupt sources. Writing any
of these bits with 1 clears that interrupt.
Bit [7:4]:
Reserved
Bit 3:
Cap1 Fall Active
0 = No event
1 = A falling edge has occurred on Cap1
Bit 2:
Cap1 Rise Active
0 = No event
1 = A rising edge has occurred on Cap1
Bit 1:
Cap0 Fall Active
0 = No event
1 = A falling edge has occurred on Cap0
Bit 0:
Cap0 Rise Active
0 = No event
1 = A rising edge has occurred on Cap0
Note:
The interrupt status bits must be cleared by firmware to enable subsequent interrupts. This is achieved by writing a ‘1’ to
the corresponding Interrupt status bit.
Table 76.Programmable Interval Timer Low (PITMRL) [0x26] [R]
Bit #
7
6
5
4
3
2
1
0
Field
Prog Interval Timer [7:0]
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Prog Interval Timer [7:0]
This register holds the low order-byte of the 12-bit programmable interval timer. Reading this register causes the high-order byte
to be moved into a holding register allowing an automatic read of all 12 bits simultaneously.
Table 77.Programmable Interval Timer High (PITMRH) [0x27] [R]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Prog Interval Timer [11:8]
Read/Write
--
--
--
--
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit [7:4]:
Reserved
Bit [3:0]:
Prog Internal Timer [11:8]
This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order
nibble of the 12-bit timer at the instant that the low order byte was last read.
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