參數(shù)資料
型號(hào): CY7C60223
廠商: Cypress Semiconductor Corp.
英文描述: Wireless enCoRe II Microcontroller(無(wú)線enCoRe II微控制器)
中文描述: 的Wireless enCoRe II微控制器(無(wú)線enCoRe II還微控制器)
文件頁(yè)數(shù): 20/62頁(yè)
文件大?。?/td> 1276K
代理商: CY7C60223
CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 20 of 62
On the CY7C601xx, the external oscillator can be sourced by
the crystal oscillator or when the crystal oscillator is disabled it
is sourced directly from the CLKIN pin. The external crystal
oscillator is fed through the EFTB block, which can optionally
be bypassed.
CPU Clock
The CPU clock, CPUCLK, can be sourced from the external
crystal oscillator, the Internal 24 MHz Oscillator, or the Internal
32 kHz Low-power Oscillator. The selected clock source can
optionally be divided by 2
n-1
where
n
is 0–7 (see
Table 33
).
When it is not being used by the external crystal oscillator, the
CLKOUT pin can be driven from one of many sources. This is
used for test and can also be used in some applications. The
sources that can drive the CLKOUT are:
CLKIN after the optional EFTB filter
Internal 24 MHz Oscillator
Internal 32 kHz Oscillator
CPUCLK after the programmable divider
Figure 5. CPU Clock Block Diagram
SCALE
(divide by 2
n,
n = 0-5,7)
MUX
CLK_EXT
CLK_24MHz
CPUCLK
SEL
CLK_CPU
Doubler
CLK_HS
LP OSC
32-KHz
CLK_32KHz
XTAL OSC
1-24MHz
CY7C601xx only
MUX
Crystal Oscillator Disabled
XOSC
SEL
EN
CLK_EXT
EFTB
P0.0
CLKIN
P0.1
CLKOUT
CY7C601xx
only
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