參數(shù)資料
型號: CY7C60223
廠商: Cypress Semiconductor Corp.
英文描述: Wireless enCoRe II Microcontroller(無線enCoRe II微控制器)
中文描述: 的Wireless enCoRe II微控制器(無線enCoRe II還微控制器)
文件頁數(shù): 43/62頁
文件大小: 1276K
代理商: CY7C60223
CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 43 of 62
SPI Interface Pins
The SPI interface uses the P1.3–P1.6 pins. These pins are
configured using the P1.3 and P1.4–P1.6 Configuration.
Timer Registers
All timer functions of the enCoRe II LV are provided by a single
timer block. The timer block is asynchronous from the CPU
clock. The 16-bit free-running counter is used as the time-base
for timer captures and can also be used as a general time-
base by software.
Registers
Free-running Counter
The 16 bit free-running counter is clocked by the Timer
Capture Clock (TCAPCLK). It can be read in software for use
as a general-purpose time base. When the low-order byte is
read, the high-order byte is registered. Reading the high-order
byte reads this register allowing the CPU to read the 16-bit
value atomically (loads all bits at one time). The free-running
timer generates an interrupt at 1024-
μ
s rate when clocked by
a 4 MHz source. It can also generate an interrupt when the
free-running counter overflow occurs—every 16.384 ms (with
a 4 MHz source). This allows extending the length of the timer
in software.
Figure 12. 16-bit Free Running Counter Block Diagram
Table 66.SPI SCLK Frequency
SCLK
Select
00
01
10
11
CPUCLK
Divisor
6
12
48
96
SCLK Frequency when
CPUCLK = 12 MHz
2 MHz
1 MHz
250 kHz
125 kHz
Timer Capture
Clock
16-bit Free
Running Counter
Overflow
Interrupt/Wrap
Interrupt
1024-
μ
s
Timer
Interrupt
Table 67.Free-running Timer Low-order Byte (FRTMRL) [0x20] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Free Running Timer [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:0]:
Free-running Timer [7:0]
This register holds the low-order byte of the 16-bit free-running timer. Reading this register causes the high-order byte to be
moved into a holding register allowing an automatic read of all 16 bits simultaneously.
For reads, the actual read occurs in the cycle when the low order is read. For writes the actual time the write occurs is the cycle
when the high order is written.
When reading the Free-running Timer, the low-order byte should be read first and the high-order second. When writing, the low-
order byte should be written first then the high-order byte.
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