參數(shù)資料
型號： CY7C60223
廠商： Cypress Semiconductor Corp.
英文描述： Wireless enCoRe II Microcontroller(無線enCoRe II微控制器)
中文描述： 的Wireless enCoRe II微控制器（無線enCoRe II還微控制器）
文件頁數(shù)： 29/62頁
文件大小： 1276K
代理商： CY7C60223
CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 29 of 62
Figure 8. Sleep Timing
Wakeup Sequence
Once asleep, the only event that can wake the system up is
an interrupt. The global interrupt enable of the CPU flag
register does not need to be set. Any unmasked interrupt will
wake the system up. It is optional for the CPU to actually take
the interrupt after the wakeup sequence. The wakeup
sequence is synchronized to the 32 kHz clock for purposes of
sequencing a startup delay, to allow the Flash memory module
enough time to power up before the CPU asserts the first read
access. Another reason for the delay is to allow the oscillator,
Bandgap, and LVD/POR circuits time to settle before actually
being used in the system. As shown in
Figure 9
, the wakeup
sequence is as follows:
1. The wakeup interrupt occurs and is synchronized by the
negative edge of the 32 kHz clock.
2. At the following positive edge of the 32 kHz clock, the
system wide PD signal is negated. The Flash memory
module, internal oscillator, EFTB, and bandgap circuit are
all powered up to a normal operating state.
3. At the following positive edge of the 32 kHz clock, the
current values for the precision POR and LVD have settled
and are sampled.
4. At the following negative edge of the 32 kHz clock (after
about 15 μs nominal), the BRQ signal is negated by the
sleep logic circuit. On the following CPUCLK, BRA is
negated by the CPU and instruction execution resumes.
Note that in
Figure 9
fixed function blocks, such as Flash,
internal oscillator, EFTB, and bandgap, have about 15 μs
start up. The wakeup times (interrupt to CPU operational)
will range from 75 μs to 105 μs.
Firmware write to SCR
SLEEP bit causes an
immediate BRQ
IOW
SLEEP
BRQ
PD
BRA
CPUCLK
CPU captures
BRQ on next
CPUCLK edge
CPU
responds
with a BRA
On the falling edge of
CPUCLK, PD is asserted.
The 24/48 MHz system clock
is halted; the Flash and
bandgap are powered down
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C60223-3X14C 制造商:Cypress Semiconductor 功能描述:CY7C60223-3X14C - Bulk 制造商:Cypress Semiconductor 功能描述:USB
CY7C60223-3XWC 制造商:Cypress Semiconductor 功能描述:USB - Bulk 制造商:Cypress Semiconductor 功能描述:Bulk / RF Companion Microcontrollers
CY7C60223-PXC 功能描述:IC MCU 8K WIRELESS 24-DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:enCoRe™ II CY7C602xx 標準包裝:60 系列:PSOC® 3 CY8C38xx 核心處理器:8051 芯體尺寸:8-位 速度:67MHz 連通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外圍設備:電容感應，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):25 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 電壓 - 電源 (Vcc/Vdd):1.71 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 2x20b，D/A 4x8b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFQFN 裸露焊盤 包裝:托盤
CY7C60223-QXC 功能描述:8位微控制器 -MCU Wireless enCoRe II 8K Flash 256 RAM COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
CY7C60223-SXC 功能描述:8位微控制器 -MCU Wireless enCoRe II 8K Flash 256 RAM COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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