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參數(shù)資料
| 型號： | CY7C60123 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| 中文描述： | 的Wireless enCoRe II微控制器（無線enCoRe II還微控制器） |
| 文件頁數(shù)： | 50/62頁 |
| 文件大小： | 1276K |
| 代理商： | CY7C60123 |
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CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 50 of 62
Interrupt Processing
The sequence of events that occur during interrupt processing
is as follows:
1. An interrupt becomes active, either because:
a. The interrupt condition occurs (e.g., a timer expires).
b. A previously posted interrupt is enabled through an
update of an interrupt mask register.
c. An interrupt is pending and GIE is set from 0 to 1 in the
CPU Flag register.
2. The current executing instruction finishes.
3. The internal interrupt is dispatched, taking 13 cycles. During
this time, the following actions occur:
a. The MSB and LSB of Program Counter and Flag
registers (CPU_PC and CPU_F) are stored onto the
program stack by an automatic CALL instruction (13
cycles) generated during the interrupt acknowledge
process.
b. The PCH, PCL, and Flag register (CPU_F) are stored
onto the program stack (in that order) by an automatic
CALL instruction (13 cycles) generated during the
interrupt acknowledge process.
c. The CPU_F register is then cleared. Since this clears the
GIE bit to 0, additional interrupts are temporarily
disabled.
d. The PCH (PC[15:8]) is cleared to zero.
e. The interrupt vector is read from the interrupt controller
and its value placed into PCL (PC[7:0]). This sets the
program counter to point to the appropriate address in
the interrupt table (e.g., 0004h for the POR/LVD
interrupt).
4. Program execution vectors to the interrupt table. Typically,
a LJMP instruction in the interrupt table sends execution to
the user's Interrupt Service Routine (ISR) for this interrup0t.
5. The ISR executes. Note that interrupts are disabled since
GIE = 0. In the ISR, interrupts can be re-enabled if desired
by setting GIE = 1 (care must be taken to avoid stack
overflow).
6. The ISR ends with a RETI instruction which restores the
Program Counter and Flag registers (CPU_PC and
CPU_F). The restored Flag register re-enables interrupts,
since GIE = 1 again.
7. Execution resumes at the next instruction, after the one that
occurred before the interrupt. However, if there are more
pending interrupts, the subsequent interrupts will be
processed before the next normal program instruction.
Interrupt Latency
The time between the assertion of an enabled interrupt and the
start of its ISR can be calculated from the following equation.
Latency = Time for current instruction to finish + Time for
internal interrupt routine to execute + Time for LJMP
instruction in interrupt table to execute.
For example, if the 5-cycle JMP instruction is executing when
an interrupt becomes active, the total number of CPU clock
cycles before the ISR begins would be as follows:
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt
routine) + (7 cycles for LJMP) = 21 to 25 cycles.
In the example above, at 12 MHz, 25 clock cycles take 2.08 μs.
Interrupt Registers
Interrupt Clear Register
The Interrupt Clear Registers (INT_CLRx) are used to enable
the individual interrupt sources’ ability to clear posted inter-
rupts.
When an INT_CLRx register is read, any bits that are set
indicates an interrupt has been posted for that hardware
resource. Therefore, reading these registers gives the user the
ability to determine all posted interrupts.
Table 81. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
GPIO Port 1
Sleep Timer
INT1
GPIO Port 0
SPI Receive
SPI Transmit
INT0
POR/LVD
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C60123-3X14C | 制造商:Cypress Semiconductor 功能描述:CY7C60123-3X14C - Bulk 制造商:Cypress Semiconductor 功能描述:USB |
| CY7C60123-3XWC | 制造商:Cypress Semiconductor 功能描述:USB - Bulk |
| CY7C60123-PVXC | 功能描述:8位微控制器 -MCU 8K Flash 256byte RAM 48 COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C60123-PVXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C60123-PXC | 功能描述:8位微控制器 -MCU 8K Flash 256byte RAM 48 COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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