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參數(shù)資料
| 型號： | CY7C60123 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| 中文描述： | 的Wireless enCoRe II微控制器（無線enCoRe II還微控制器） |
| 文件頁數(shù)： | 28/62頁 |
| 文件大?。?/td> | 1276K |
| 代理商： | CY7C60123 |
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CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 28 of 62
Sleep Mode
The CPU can only be put to sleep by the firmware. This is
accomplished by setting the Sleep bit in the System Status and
Control Register (CPU_SCR). This stops the CPU from
executing instructions, and the CPU will remain asleep until an
interrupt comes pending, or there is a reset event (either a
Power-on Reset, or a Watchdog Timer Reset).
The Low-voltage Detection circuit (LVD) drops into fully
functional power-reduced states, and the latency for the LVD
is increased. The actual latency can be traded against power
consumption by changing Sleep Duty Cycle field of the
ECO_TR Register.
The Internal 32 kHz Low-speed Oscillator remains running.
Prior to entering suspend mode, firmware can optionally
configure the 32 kHz Low-speed Oscillator to operate in a low-
power mode to help reduce the over all power consumption
(using the 32 kHz Low Power bit,
Table 38
). This will help save
approximately 5
μ
A; however, the trade off is that the 32 kHz
Low-speed Oscillator will be less accurate (–53.12% to
+56.25% deviation).
All interrupts remain active. Only the occurrence of an interrupt
will wake the part from sleep. The Stop bit in the System Status
and Control Register (CPU_SCR) must be cleared for a part
to resume out of sleep. The Global Interrupt Enable bit of the
CPU Flags Register (CPU_F) does not have any effect. Any
unmasked interrupt will wake the system up. As a result, any
interrupts not intended for waking should be disabled through
the Interrupt Mask Registers.
When the CPU enters sleep mode the CPUCLK Select (Bit 1,
Table 32
) is forced to the Internal Oscillator. The internal oscil-
lator recovery time is three clock cycles of the Internal 32 kHz
Low-power Oscillator. The Internal 24 MHz Oscillator restarts
immediately on exiting Sleep mode. If the external crystal
oscillator is used, firmware will need to switch the clock source
for the CPU.
Unlike the Internal 24 MHz Oscillator, the external oscillator is
not automatically shut-down during sleep. Systems that need
the external oscillator disabled in sleep mode will need to
disable the external oscillator prior to entering sleep mode. In
systems where the CPU runs off the external oscillator,
firmware will need to switch the CPU to the internal oscillator
prior to disabling the external oscillator.
On exiting sleep mode, once the clock is stable and the delay
time has expired, the instruction immediately following the
sleep instruction is executed before the interrupt service
routine (if enabled).
The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintaining
very low average power consumption. The Sleep interrupt
may also be used to provide periodic interrupts during non-
sleep modes.
Sleep Sequence
The SLEEP bit is an input into the sleep logic circuit. This
circuit is designed to sequence the device into and out of the
hardware sleep state. The hardware sequence to put the
device to sleep is shown in
Figure 8
and is defined as follows.
1. Firmware sets the SLEEP bit in the CPU_SCR0 register.
The Bus Request (BRQ) signal to the CPU is immediately
asserted. This is a request by the system to halt CPU op-
eration at an instruction boundary. The CPU samples BRQ
on the positive edge of CPUCLK.
2. Due to the specific timing of the register write, the CPU
issues a Bus Request Acknowledge (BRA) on the following
positive edge of the CPU clock. The sleep logic waits for
the following negative edge of the CPU clock and then
asserts a system-wide Power Down (PD) signal. In
Figure 8
the CPU is halted and the system-wide power down signal
is asserted.
3. The system-wide PD (power down) signal controls several
major circuit blocks: The Flash memory module, the internal
24-MHz oscillator, the EFTB filter and the bandgap voltage
reference. These circuits transition into a zero power state.
The only operational circuits on chip are the Low Power
oscillator, the bandgap refresh circuit, and the supply
voltage monitor (POR/LVD) circuit.
The external crystal oscillator on enCoRe II LV devices is not
automatically powered down when the CPU enters the sleep
state. Firmware must explicitly disable the external crystal
oscillator in order to reduce power to levels specified.
Note:
To achieve the lowest possible power consumption
during suspend/sleep, the following conditions must be
observed in addition to considerations for the sleep timer and
external crystal oscillator:
All GPIOs must be set to outputs and driven low
The port pins P1.0 and P1.1 should be configured as inputs
with their pull ups enabled.
Table 40.Reset Watchdog Timer (RESWDT) [0xE3] [W]
Bit #
7
6
5
4
3
2
1
0
Field
Reset Watchdog Timer [7:0]
Read/Write
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
Any write to this register will clear the Watchdog Timer, a write of 0x38 will also clear the Sleep Timer.
Bit [7:0]:
Reset Watchdog Timer [7:0]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C60123-3X14C | 制造商:Cypress Semiconductor 功能描述:CY7C60123-3X14C - Bulk 制造商:Cypress Semiconductor 功能描述:USB |
| CY7C60123-3XWC | 制造商:Cypress Semiconductor 功能描述:USB - Bulk |
| CY7C60123-PVXC | 功能描述:8位微控制器 -MCU 8K Flash 256byte RAM 48 COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C60123-PVXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C60123-PXC | 功能描述:8位微控制器 -MCU 8K Flash 256byte RAM 48 COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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