參數(shù)資料
型號: CY7C60123
廠商: Cypress Semiconductor Corp.
英文描述: Wireless enCoRe II Microcontroller(無線enCoRe II微控制器)
中文描述: 的Wireless enCoRe II微控制器(無線enCoRe II還微控制器)
文件頁數(shù): 22/62頁
文件大小: 1276K
代理商: CY7C60123
CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 22 of 62
Interval Timer Clock (ITMRCLK)
The Interval Timer clock (ITMRCLK), can be sourced from the
external crystal oscillator, the Internal 24 MHz Oscillator, the
Internal 32 kHz Low-power Oscillator, or the Timer Capture
clock. A programmable prescaler of 1, 2, 3, 4 then divides the
selected source. The 12-bit Programmable Interval Timer is a
simple down counter with a programmable reload value. It
provides a 1-
μ
s resolution by default. When the down counter
reaches zero, the next clock is spent reloading. The reload
value can be read and written while the counter is running, but
care should be taken to ensure that the counter does not
unintentionally reload while the 12-bit reload value is only
partially stored—i.e., between the two writes of the 12-bit
value. The Programmable interval timer generates an interrupt
to the CPU on each reload.
The parameters to be set will show up on the device editor
view of PSoC Designer once you place the enCoRe II LV timer
user module. The parameters are PITIMER_Source and
PITIMER_Divider. The PITIMER_Source is the clock to the
timer and the PITIMER_Divider is the value the clock is divided
by.
The interval register (PITMR) holds the value that is loaded
into the PIT counter on terminal count.
The Programmable Interval Timer resolution is configurable.
For example:
TCAPCLK divide by x of CPU clock (for example TCAPCLK
divide by 2 of a 24 MHz CPU clock will give a frequency of
12 MHz)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK
divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25
μ
s)
Table 34.Clock I/O Config (CLKIOCR) [0x32] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
XOSC
Select
XOSC
Enable
EFTB
Disabled
CLKOUT Select
Read/Write
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:5]:
Reserved
Bit 4:
XOSC Select
This bit, when set, selects the external crystal oscillator clock as clock source of external clock. Care needs to be taken while
selecting the crystal oscillator clock. First enable the crystal oscillator and wait for few cycles, which is oscillator stabilization
period. Then select the crystal clock as clock source. Similarly, while deselect crystal clock, first deselect crystal clock as clock
source then disable the crystal oscillator
0 = Not select external crystal oscillator clock
1 = Select the external crystal oscillator clock
Bit 3:
XOSC Enable
This bit is only available on the CY7C601xx
This bit when set enables the external crystal oscillator. The external crystal oscillator shares pads CLKIN and CLKOUT with
two GPIOs—P0.0 and P0.1, respectively. When the external crystal oscillator is enabled, the CLKIN signal comes from the
external crystal oscillator block and the output enables on the GPIOs for P0.0 and P0.1 are disabled, eliminating the possibility
of contention. When the external crystal oscillator is disabled the source for CLKIN signal comes from the P0.0 GPIO input.
0 = Disable the external oscillator
1 = Enable the external oscillator
Note:
The external crystal oscillator start-up time takes up to 2 ms.
Bit 2:
EFTB Disabled
This bit is only available on the CY7C601xx.
0 = Enable the EFTB filter
1 = Disable the EFTB filter, causing CLKIN to bypass the EFTB filter
Bit [1:0]:
CLKOUT Select
0 0 = Internal 24 MHz Oscillator
0 1 = External crystal oscillator – external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled,
CLKIN input if the external oscillator is disabled.
1 0 = Internal 32 kHz Low-power Oscillator
1 1 = CPUCLK
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