參數(shù)資料
型號： CY7C60123
廠商： Cypress Semiconductor Corp.
英文描述： Wireless enCoRe II Microcontroller(無線enCoRe II微控制器)
中文描述： 的Wireless enCoRe II微控制器（無線enCoRe II還微控制器）
文件頁數(shù)： 32/62頁
文件大小： 1276K
代理商： CY7C60123
CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 32 of 62
ECO Trim Register
General Purpose I/O Ports
Port Data Registers
P0 Data
Table 43.ECO (ECO_TR) [0x1EB] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Sleep Duty Cycle [1:0]
Reserved
Read/Write
R/W
R/W
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
This register controls the ratios (in numbers of 32 kHz clock periods) of “on” time versus “off” time for LVD and POR detection
circuit.
Bit [7:6]:
Sleep Duty Cycle [1:0]
0 0 = 128 periods of the Internal 32 kHz Low-speed Oscillator
0 1 = 512 periods of the Internal 32 kHz Low-speed Oscillator
1 0 = 32 periods of the Internal 32 kHz Low-speed Oscillator
1 1 = 8 periods of the Internal 32 kHz Low-speed Oscillator
Note:
This register can only be accessed in the second bank of I/O space. This requires setting the XIO bit in the CPU flags
register.
Table 44.P0 Data Register (P0DATA)[0x00] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
P0.7
P0.6/TIO1
P0.5/TIO0
P0.4/INT2
P0.3/INT1
P0.2/INT0
P0.1/CLKOUT
P0.0/CLKIN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 0 pins.
Bit 7:
P0.7 Data
Bit [6:5]:
P0.6–P0.5 Data/TIO1 and TIO0
Beside their use as the P0.6–P0.5 GPIOs, these pins can also be used for the alternate functions as the Capture Timer input or
Timer output pins (TIO1 and TIO0). To configure the P0.5 and P0.6 pins, refer to the P0.5/TIO0–P0.6/TIO1 Configuration Register
(
Table 52
.)
Bit [4:2]:
P0.4–P0.2 Data/INT2–INT0
Beside their use as the P0.4–P0.2 GPIOs, these pins can also be used for the alternate functions as the Interrupt pins
(INT0–INT2). To configure the P0.4–P0.2 pins, refer to the P0.2/INT0–P0.4/INT2 Configuration Register (
Table 51
)
Bit 1:
P0.1/CLKOUT
Beside its use as the P0.1 GPIO, this pin can also be used for the alternate function as the CLK OUT pin. To configure the P0.1
pin, refer to the P0.1/CLKOUT Configuration Register (
Table 50
.)
Bit 0:
P0.0/CLKIN
Beside its use as the P0.0 GPIO, this pin can also be used for the alternate function as the CLKIN pin. To configure the P0.0
pin, refer to the P0.0/CLKIN Configuration Register (
Table 49
.)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C60123-3X14C 制造商:Cypress Semiconductor 功能描述:CY7C60123-3X14C - Bulk 制造商:Cypress Semiconductor 功能描述:USB
CY7C60123-3XWC 制造商:Cypress Semiconductor 功能描述:USB - Bulk
CY7C60123-PVXC 功能描述:8位微控制器 -MCU 8K Flash 256byte RAM 48 COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C60123-PVXCKJ 制造商:Cypress Semiconductor 功能描述:
CY7C60123-PXC 功能描述:8位微控制器 -MCU 8K Flash 256byte RAM 48 COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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