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CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C
Page 15 of 62
Data Memory Organization
The CY7C601xx/CY7C602xx microcontrollers provide up to 256 bytes of data RAM
Figure 4. Data Memory Organization
Flash
This section describes the Flash block of the enCoRe II LV.
Much of the user-visible Flash functionality, including
programming and security, are implemented in the M8C
Supervisory Read Only Memory (SROM). enCoRe II LV Flash
has an endurance of 1000 erase/write cycles and a 10-year
data retention capability.
Flash Programming and Security
All Flash programming is performed by code in the SROM. The
registers that control the Flash programming are only visible
to the M8C CPU when it is executing out of SROM. This makes
it impossible to read, write, or erase the Flash by bypassing
the security mechanisms implemented in the SROM.
Customer firmware can only program the Flash via SROM
calls. The data or code images can be sourced via any
interface with the appropriate support firmware. This type of
programming requires a ‘boot-loader’—a piece of firmware
resident on the Flash. For safety reasons this boot-loader
should not be overwritten during firmware rewrites.
The Flash provides four extra auxiliary rows that are used to
hold Flash block protection flags, boot time calibration values,
configuration tables, and any device values. The routines for
accessing these auxiliary rows are documented in the SROM
section. The auxiliary rows are not affected by the device
erase function.
In-System Programming
enCoRe II LV devices enable this type of in-system
programming by using the P1.0 and P1.1 pins as the serial
programming mode interface. This allows an external
controller to cause the enCoRe II LV part to enter serial
programming mode and then to use the test queue to issue
Flash access functions in the SROM.
SROM
The SROM holds code that is used to boot the part, calibrate
circuitry, and perform Flash operations (
Table 20
lists the
SROM functions). The functions of the SROM may be
accessed in normal user code or operating from Flash. The
SROM exists in a separate memory space from user code.
The SROM functions are accessed by executing the Super-
visory System Call instruction (SSC), which has an opcode of
00h. Prior to executing the SSC the M8C’s accumulator needs
to be loaded with the desired SROM function code from
Table 20
. Undefined functions will cause a HALT if called from
user code. The SROM functions are executing code with calls;
therefore, the functions require stack space. With the
exception of Reset, all of the SROM functions have a
parameter block
in SRAM that must be configured before
executing the SSC.
Table 21
lists all possible parameter block
variables. The meaning of each parameter, with regards to a
specific SROM function, is described later in this chapter
.
after reset
8-bit PSP
Address
0x00
Stack begins here and grows upward
Top of RAM Memory
0xFF
Table 20.SROM Function Codes
Function Code
00h
01h
02h
03h
05h
06h
07h
Function Name
SWBootReset
ReadBlock
WriteBlock
EraseBlock
EraseAll
TableRead
CheckSum
Stack Space
0
7
10
9
11
3
3