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參數(shù)資料
| 型號(hào)： | CY7C43644 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 每1000 x36 x2雙向同步FIFO瓦特/總線匹配（每1000 x36 x2雙向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 7/37頁 |
| 文件大小： | 581K |
| 代理商： | CY7C43644 |
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
7
PRELIMINARY
AC Test Loads and Waveforms (-10 & -15)
AC Test Loads and Waveforms (-7)
3.0V
5V
OUTPUT
R2=680
C
L
=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
R1=1.1K
3.0V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
I/O
50
V
CC
/2
Z0=50
Switching Characteristics
Over the Operating Range
Parameter
Description
CY7C43624/
34/44/64/84
–
7
Min.
CY7C43624/
34/44/64/84
–
10
Min.
CY7C43624/
34/44/64/84
–
15
Min.
Unit
Max.
Max.
Max.
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
Clock Frequency, CLKA or CLKB
133
100
67
MHz
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
Pulse Duration, CLKA or CLKB LOW
Set-Up Time, A
0
–
35
before CLKA
↑
and B
0
–
35
before CLKB
↑
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA
↑
; CSB, W/RB, ENB, and MBB before
CLKB
↑
Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW
before CLKA
↑
or CLKB
↑
[7]
Set-Up Time, FS0 and FS1 before MRS1 and
MRS2 HIGH
3.5
4
6
ns
3
4
5
ns
t
ENS
3
4
5
ns
t
RSTS
2.5
4
5
ns
t
FSS
5
7
7.5
ns
t
BES
Set-Up Time, BE/FWFT before MRS1 and MRS2
HIGH
5
7
7.5
ns
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
Set-Up Time, SPM before MRS1 and MRS2 HIGH
Set-Up Time, FS0/SD before CLKA
↑
Set-Up Time, FS1/SEN before CLKA
↑
Set-Up Time, BE/FWFT before CLKA
↑
Hold Time, A
0
–
35
after CLKA
↑
and B
0
–
35
after
CLKB
↑
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA
↑
; CSB, W/RB, ENB, and MBB after CLKB
↑
5
7
7.5
ns
3
4
5
ns
3
4
5
ns
0
0
0
ns
0
0
0
ns
t
ENH
0
0
0
ns
Note:
7.
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43664 | 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43684 | 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43636 | 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進(jìn)先出) |
| CY7C43626 | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43644AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 128-Pin TQFP |
| CY7C43663-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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