參數(shù)資料
型號： CY7C43644
廠商： Cypress Semiconductor Corp.
英文描述： 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
中文描述： 每1000 x36 x2雙向同步FIFO瓦特/總線匹配（每1000 x36 x2雙向同步先進(jìn)先出帶總線匹配）
文件頁數(shù)： 30/37頁
文件大?。?/td> 581K
代理商： CY7C43644
CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
30
PRELIMINARY
write pointer and read pointer comparator that indicates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cy-
cles have not elapsed since the time the word was written. The
Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs, si-
multaneously forcing the Output Ready flag HIGH and shifting
the word to the FIFO output register.
In the CY Standard mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data avail-
able for reading in a minimum of two cycles of the Empty flag
synchronizing clock. Therefore, an Empty flag is LOW if a word
in memory is the next data to be sent to the FIFO output reg-
ister and two cycles have not elapsed since the time the word
was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock
occurs, forcing the Empty flag HIGH; only then can data be
read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time t
SKEW1
or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT mode, the Input Ready
(IRA and IRB) function is selected. In CY Standard mode, the
Full Flag (FFA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a Full/
Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is full,
full
–
1, or full
–
2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the read sets the Full/
Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time t
SKEW1
or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X1 for AEB and register X2 for AEA. These registers are load-
ed with preset values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost Empty flag and
Almost Full flag offset programming above). An Almost Empty
flag is LOW when its FIFO contains X or less words and is
HIGH when its FIFO contains (X+1) or more words. A data
word present in the FIFO output register has been read from
memory.
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty flag to reflect the new level of fill. Therefore, the Almost
Full flag of a FIFO containing (X+1) or more words remains
LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to the (X+1) level. A LOW-to-HIGH transition of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time t
SKEW2
or greater after
the write that fills the FIFO to (X+1) words. Otherwise, the sub-
sequent synchronizing clock cycle may be the first synchroni-
zation cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a write pointer and read pointer com-
parator that indicates when the FIFO SRAM status is almost
full, almost full
–
1, or almost full
–
2. The Almost Full state is
defined by the contents of register Y1 for AFA and register Y2
for AFB. These registers are loaded with preset values during
a FIFO reset, programmed from Port A, or programmed seri-
ally (see Almost Empty flag and Almost Full flag offset pro-
gramming above). An Almost Full flag is LOW when the num-
ber of words in its FIFO is greater than or equal to (256
–
Y),
(512
–
Y), (1024
–
Y), (4096
–
Y), or (16384
–
Y) for the
CY7C436X4 respectively. An Almost Full flag is HIGH when
the number of words in its FIFO is less than or equal to
[256
–
(Y+1)], [512
–
(Y+1)], [1024
–
(Y+1)], [4096
–
(Y+1)], or
[16384
–
(Y+1)], for the CY7C436X4 respectively. Note that a
data word present in the FIFO output register has been read
from memory.
Two LOW-to-HIGH transitions of the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [256/512/1024/4096/16384
–
(Y+1)]
or less words remains LOW if two cycles of its synchronizing
clock have not elapsed since the read that reduced the number
of words in memory to [256/512/1024/4096/16384
–
(Y+1)]. An
Almost Full flag is set HIGH by the second LOW-to-HIGH tran-
sition of its synchronizing clock after the FIFO read that reduc-
es the number of words in memory to [256/512/1024/4096/
16384
–
(Y+1)]. A LOW-to-HIGH transition of an Almost Full
flag synchronizing clock begins the first synchronization cycle
if it occurs at time t
SKEW2
or greater after the read that reduces
the number of words in memory to [256/512/1024/4096/
16384
–
(Y+1)]. Otherwise, the subsequent synchronizing clock
cycle may be the first synchronization cycle.
相關(guān)PDF資料
PDF描述
CY7C43664 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43684 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43636 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進(jìn)先出)
CY7C43626 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出)
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43644AV-10AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 128-Pin TQFP
CY7C43663-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43664-7AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43682-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43683-10AI 制造商:Rochester Electronics LLC 功能描述:- Bulk
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