參數(shù)資料
型號(hào): CY7C43644
廠商: Cypress Semiconductor Corp.
英文描述: 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
中文描述: 每1000 x36 x2雙向同步FIFO瓦特/總線匹配(每1000 x36 x2雙向同步先進(jìn)先出帶總線匹配)
文件頁(yè)數(shù): 22/37頁(yè)
文件大小: 581K
代理商: CY7C43644
CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
22
PRELIMINARY
Notes:
33. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long-word, respectively.
34. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[34]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO2 Output Register
Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A
0
35
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B
0
35
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
[33]
相關(guān)PDF資料
PDF描述
CY7C43664 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43684 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43636 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進(jìn)先出)
CY7C43626 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出)
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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